High-k dielectric materials utilized in display devices

Abstract

Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure includes source and drain electrodes formed on a substrate, a gate insulating layer formed on a substrate covering the source and drain electrodes, wherein the gate insulating layer is a high-k material having a dielectric constant greater than 10, and a gate electrode formed above or below the gate insulating layer.

What is claimed is: 
     
         1 . A thin film transistor structure comprising:
 source and drain electrodes formed on a substrate;   a gate insulating layer formed on a substrate covering the source and drain electrodes, wherein the gate insulating layer is a high-k material having a dielectric constant greater than 10; and   a gate electrode formed above or below the gate insulating layer.   
     
     
         2 . The structure of  claim 1 , further comprising:
 a capacitor layer formed on the gate electrode, wherein the capacitor layer is fabricated from a high-k material having a dielectric constant greater than 10.   
     
     
         3 . The structure of  claim 2 , wherein the high-k material of the gate insulating layer or the capacitor layer is formed by an atomic layer deposition process. 
     
     
         4 . The structure of  claim 1 , wherein the high-k material is at least one of hafnium dioxide (HfO 2 ), hafnium oxynitride (HfON), zirconium dioxide (ZrO 2 ), zirconium oxynitride (ZrON), aluminum oxide (Al 2 O 3 ), aluminum oxynitride (AlON), hafnium silicon oxide (HfSiO 2 ), hafnium aluminum oxide (HfAlO), zirconium silicon oxide (ZrSiO 2 ), tantalum dioxide (Ta 2 O 5 ), aluminum oxide, Y 2 O 3 , La 2 O 3 , titanium oxide (TiO 2 ), aluminum doped hafnium dioxide, bismuth strontium titanium (BST), or platinum zirconium titanium (PZT). 
     
     
         5 . The structure of  claim 1 , wherein the gate insulating layer comprises a bulk gate insulating layer formed on a bottom dielectric layer. 
     
     
         6 . The method of  claim 5 , wherein the gate insulating layer further comprises a top dielectric layer formed on the bulk gate insulating layer disposed on the bottom dielectric layer. 
     
     
         7 . The structure of  claim 6 , wherein the bulk gate insulating layer is formed by a high-k material and the top and bottom dielectric layer is formed by a silicon containing material. 
     
     
         8 . The structure of  claim 6 , wherein the silicon containing material is formed by a plasma enhanced chemical vapor deposition process, a MOCVD or ALD process. 
     
     
         9 . The structure of  claim 2 , wherein the capacitor further comprises a bulk capacitor layer formed on a bottom dielectric layer. 
     
     
         10 . The structure of  claim 9 , wherein the capacitor layer further comprises a top dielectric layer formed on the bulk capacitor layer formed on the bottom dielectric layer. 
     
     
         11 . The structure of  claim 2 , further comprising:
 an insulating layer formed between a common electrode and a pixel electrode disposed on the interlayer insulator, wherein the insulating layer, the common electrode and the pixel electrode in combination form a capacitor, wherein the insulating layer is a high-k material fabricated by an atomic layer deposition process.   
     
     
         12 . The structure of  claim 11 , further comprising:
 a passivation layer formed on the capacitor, wherein the passivation layer is a high-k material fabricated from an atomic layer deposition process.   
     
     
         13 . A method of forming a capacitor layer in display devices, comprising:
 performing an atomic layer deposition process to form a capacitor layer on a substrate, wherein the capacitor layer has a dielectric constant greater than 10, wherein the capacitor layer is formed between two electrodes utilized in a thin film transistor device or an OLED device.   
     
     
         14 . The method of  claim 13 , further comprising:
 performing a plasma enhanced chemical vapor deposition process prior to the atomic layer deposition process to form a silicon containing layer between the electrode and the capacitor layer.   
     
     
         15 . The method of  claim 13 , further comprising:
 performing a chemical vapor deposition process to form a silicon containing layer on the capacitor layer.   
     
     
         16 . The method of  claim 13 , wherein the capacitor layer is a gate insulating layer, an interlayer insulator, an insulating layer, or a passivation layer in a TFT device. 
     
     
         17 . The method of  claim 13 , wherein the capacitor layer and the two electrodes form a storage capacitor in display devices. 
     
     
         18 . A method for forming a hybrid layer in display devices, comprising:
 forming a hybrid layer in display devices, wherein the hybrid layer includes a first dielectric layer formed by a chemical vapor deposition process and a second dielectric layer formed by an atomic layer deposition process, wherein the hybrid layer is formed as a capacitor layer or a gate insulating layer in the display devices.   
     
     
         19 . The method of  claim 18 , wherein the hybrid layer comprises a high-k material having a dielectric constant greater than 10. 
     
     
         20 . The method of  claim 19 , wherein the high-k material is at least one of hafnium dioxide (HfO 2 ), hafnium oxynitride (HfON), zirconium dioxide (ZrO 2 ), zirconium oxynitride (ZrON), aluminum oxide (Al 2 O 3 ), aluminum oxynitride (AlON), hafnium silicon oxide (HfSiO 2 ), hafnium aluminum oxide (HfAlO), zirconium silicon oxide (ZrSiO 2 ), tantalum dioxide (Ta 2 O 5 ), aluminum oxide, Y 2 O 3 , La 2 O 3 , titanium oxide (TiO 2 ), aluminum doped hafnium dioxide, bismuth strontium titanium (BST), or platinum zirconium titanium (PZT).