Transistor fabrication technique including sacrificial protective layer for source/drain at contact location

Abstract

Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently, after contact trench etch is performed, an additional etch process may be performed to remove the sacrificial protective layer and expose a clean S/D surface. Thus, the sacrificial protective layer can protect the contact locations of the S/D regions from contamination (e.g., oxidation or nitridation) caused by insulator layer deposition. The sacrificial protective layer can also protect the S/D regions from undesired insulator material remaining on the S/D contact surface, particularly for non-planar transistor structures (e.g., finned or nanowire/nanoribbon transistor structures).

What is claimed is: 
     
         1 . An integrated circuit (IC) including at least one transistor, the IC comprising:
 a channel region;   a gate structure at least above the channel region;   a source region adjacent the channel region;   a drain region adjacent the channel region;   a first contact at least above the source region, the first contact in electrical contact with the source region;   a second contact at least above the drain region, the second contact in electrical contact with the drain region;   a layer on a portion of the source region and on a portion of the drain region, the layer absent between the source region and the first contact, the layer also absent between the drain region and the second contact, wherein the layer includes at least one of titanium and aluminum; and   an insulator layer on the layer, wherein the insulator layer includes compositionally different material from the layer.   
     
     
         2 . The IC of  claim 1 , wherein the layer includes only one of titanium and aluminum. 
     
     
         3 . The IC of  claim 2 , wherein the layer essentially consists of titanium and nitrogen. 
     
     
         4 . The IC of  claim 2 , wherein the layer essentially consists of aluminum and oxygen. 
     
     
         5 . The IC of  claim 1 , wherein the insulator layer includes silicon. 
     
     
         6 . The IC of  claim 5 , wherein the insulator layer essentially consists of at least two of silicon, oxygen, nitrogen, and carbon. 
     
     
         7 . The IC of  claim 1 , wherein the layer has an etch rate that is at least three times greater than an etch rate of the insulator layer for a given etch scheme. 
     
     
         8 . The IC of  claim 1 , wherein the layer is less than 100 angstroms thick. 
     
     
         9 . The IC of  claim 1 , further comprising another insulator layer on the insulator layer, the other insulator layer compositionally different from the layer, the other insulator layer also compositionally different from the insulator layer. 
     
     
         10 . The IC of  claim 1 , wherein at least a portion of the source region is also between two portions of the first contact and at least a portion of the drain region is also between two portions of the second contact. 
     
     
         11 . The IC of  claim 1 , wherein the channel region includes a finned configuration, such that in addition to the gate structure being above the channel region, the channel region is also between two portions of the gate structure so as to provide a multigate structure. 
     
     
         12 . The IC of  claim 1 , wherein the channel region includes a nanowire configuration, such that the gate structure surrounds one or more nanowires included in the channel region. 
     
     
         13 . A computing system comprising the IC of  claim 1 . 
     
     
         14 . An integrated circuit (IC) including at least one transistor, the IC comprising:
 a non-planar channel region;   a gate structure on multiple sides of or around the channel region, the gate structure including a gate electrode and a gate dielectric, the gate dielectric between the gate electrode and the channel region;   a source region adjacent the channel region;   a drain region adjacent the channel region;   a first contact at least above the source region, the first contact in electrical contact with the source region;   a second contact at least above the drain region, the second contact in electrical contact with the drain region;   a layer on a portion of the source region and on a portion of the drain region, the layer absent between the source region and the first contact, the layer also absent between the drain region and the second contact, wherein the layer includes at least one of titanium and aluminum;   a first insulator layer on the layer; and   a second insulator layer on the first insulator layer;   wherein the layer, the first insulator layer, and the second insulator layer all include compositionally different materials.   
     
     
         15 . The IC of  claim 14 , wherein the layer essentially consists of titanium and nitrogen. 
     
     
         16 . The IC of  claim 14 , wherein the layer essentially consists of aluminum and oxygen. 
     
     
         17 . The IC of  claim 14 , wherein the first and second insulator layers each include silicon. 
     
     
         18 . A method of forming an integrated circuit (IC) including at least one transistor, the method comprising:
 forming a gate structure at least above a channel region;   forming a source region adjacent the channel region;   forming a drain region adjacent the channel region;   forming a layer on the source and drain regions, the layer including at least one of titanium and aluminum;   forming an insulator layer on the layer, the insulator layer including compositionally different material from the layer;   forming a first contact at least above the source region and in a first contact trench, the forming of the first contact including removing the insulator layer and the layer from the first contact trench, such that the first contact is in direct contact with the source region; and   forming a second contact at least above the drain region and in a second contact trench, the forming of the second contact including removing the insulator layer and the layer from the second contact trench, such that the second contact in direct contact with the drain region.   
     
     
         19 . The method of  claim 18 , wherein the layer includes only one of titanium and aluminum. 
     
     
         20 . The method of  claim 18 , wherein removing the layer from the first and second contact trenches includes using sulfuric acid to expose at least a portion of the respective source and drain regions.