Method of forming shallow trench isolation (sti) structures

Abstract

A method of forming a trench isolation (e.g., an STI) for an integrated circuit includes forming a pad oxide layer and then a nitride layer over a semiconductor substrate, performing a trench etch through the structure to form a trench, depositing a trench oxide layer over the structure to form a filled trench, depositing a sacrificial planarizing layer, which is etch-selective to the trench oxide layer, over the deposited oxide, performing a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer, performing an oxide etch process that is selective to the trench oxide layer to remove remaining portions of the trench oxide layer outside the filled trench, and removing the remaining nitride layer such that the remaining oxide-filled trench defines a trench isolation structure that projects above an exposed upper surface of the semiconductor substrate.

1 - 15 . (canceled) 
     
     
         16 . A semiconductor die, comprising:
 a semiconductor substrate; and   a plurality of trench isolation structures formed in the semiconductor substrate by a process including:   forming a nitride layer over the semiconductor substrate;   performing a trench etch process through portions of the nitride layer and the semiconductor substrate to form a plurality of trenches;   depositing a trench oxide layer over remaining portions of the nitride layer and extending into the plurality of trenches to form a plurality of filled trenches;   depositing a sacrificial planarizing layer over the deposited oxide, the sacrificial planarizing layer being etch-selective with respect to the trench oxide layer;   performing a multi-step etch process that:   removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer; and   removes remaining portions of the trench oxide layer outside the plurality of filled trenches; and   removing the remaining portions of the nitride layer such that the remaining oxide of each filled trench defines a trench isolation structure that projects above an exposed upper surface of the semiconductor substrate.   
     
     
         17 . The semiconductor die according to  claim 16 , wherein multi-step etch process comprises:
 (c) a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer; and   (d) an oxide etch process that is selective to the trench oxide layer to remove remaining portions of the trench oxide layer outside the filled trench.   
     
     
         18 . The semiconductor die according to  claim 17 , wherein the planarizing etch process includes:
 a first etch that is selective to the planarizing layer over the trench oxide layer;   a second etch that is selective to the trench oxide layer over the planarizing layer; and   a third etch that is less selective than the first etch, wherein the second etch removes the trench oxide layer and the planarizing layer at similar rates until the planarizing layer is removed.   
     
     
         19 . The semiconductor die according to  claim 17 , wherein the oxide etch process is performed until a top surface of the oxide-filled trench is etched down to a predefined distance below a top surface of the remaining portions of the nitride layer adjacent the oxide-filled trench. 
     
     
         20 . The semiconductor die according to  claim 17 , wherein the oxide etch process is performed until a top surface of the oxide-filled trench is etched down to a predefined distance above a top surface of the semiconductor substrate adjacent the oxide-filled trench. 
     
     
         21 . The semiconductor die according to  claim 16 , wherein:
 the multi-step etch process comprises a multi-step planarizing etch process; and   the step of removing the remaining portions of the nitride layer is performed by the multi-step planarizing etch process.   
     
     
         22 . The semiconductor die according to  claim 21 , wherein multi-step etch process comprises a four-step planarizing etch process. 
     
     
         23 . The semiconductor die according to  claim 21 , wherein the multi-step planarizing etch process includes an etch selective to oxide which is performed until a top surface of the oxide-filled trench is etched down to a predefined distance above a top surface of the semiconductor substrate adjacent the oxide-filled trench. 
     
     
         24 . The semiconductor die according to  claim 16 , wherein the planarizing layer comprises an organo-siloxane based polymer. 
     
     
         25 . The semiconductor die according to  claim 16 , wherein the organosilicate comprises an organo-siloxane based polymer with the chemical formula RxCH3ySiOz, where R is an organic chromophore. 
     
     
         26 . The semiconductor die according to  claim 16 , wherein the method is performed without a chemical-mechanical planarization (CMP) process. 
     
     
         27 . A complementary metal-oxide semiconductor (CMOS) device comprising:
 a semiconductor structure comprising:   a semiconductor substrate; and   a plurality of trench isolation structures formed in the semiconductor substrate by a process including:   forming a nitride layer over the semiconductor substrate;   performing a trench etch process through portions of the nitride layer and the semiconductor substrate to form a plurality of trenches;   depositing a trench oxide layer over remaining portions of the nitride layer and extending into the plurality of trenches to form a plurality of filled trenches;   depositing a sacrificial planarizing layer over the deposited oxide, the sacrificial planarizing layer being etch-selective with respect to the trench oxide layer;   performing a multi-step etch process that:   removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer; and   removes remaining portions of the trench oxide layer outside the plurality of filled trenches; and   removing the remaining portions of the nitride layer such that the remaining oxide of each filled trench defines a trench isolation structure that projects above an exposed upper surface of the semiconductor substrate.   
     
     
         28 . The CMOS device according to  claim 27 , wherein the planarizing layer comprises an organo-siloxane based polymer.