Memory state management for electronic device

Abstract

In one embodiment a controller comprises logic to determine whether an electronic device is operating in a low power state and in response to a determination that the electronic device is operating in a low power state, implement a memory state management routine which reduces power to at least a section of volatile memory in the memory system. Other embodiments may be described.

1 . (canceled) 
     
     
         2 . A controller comprising logic to:
 determine whether an electronic device comprising a volatile memory and a nonvolatile memory is operating in a low power state; and   in response to a determination that the electronic device is operating in the low power state, determine whether a cache miss rate is below a threshold; and   in response to a determination that the cache miss rate is below the threshold:
 identify one or more sections of the volatile memory that are in a modified state; 
 relocate data only from the one or more sections of the volatile memory that are in the modified state; and 
 power down the one or more sections of the volatile memory. 
   
     
     
         3 . The controller of  claim 2 , wherein relocate data only from the one or more sections of the volatile memory further comprises relocate data only from the one or sections of the volatile memory to a section of the volatile memory. 
     
     
         4 . The controller of  claim 2 , wherein relocate data only from the one or more sections of the volatile memory further comprises relocate data only from the one or more sections of the volatile memory to the nonvolatile memory. 
     
     
         5 . The controller of  claim 2 , wherein the volatile memory is dynamic random access memory (DRAM). 
     
     
         6 . The controller of  claim 2 , wherein the volatile memory is three dimensional ( 3 D) cross point memory. 
     
     
         7 . The controller of  claim 2 , further comprising logic to:
 identify one or more sections of the volatile memory that are in an invalid state; and   suspend refresh operations to the one or more sections of the volatile memory that are in the invalid state.   
     
     
         8 . The controller of  claim 2 , wherein the one or more sections of the volatile memory that are in the modified state further comprises one or more least recently used sections of the volatile memory. 
     
     
         9 . The controller of  claim 2 , further comprising logic to:
 in response to a determination that the cache miss rate is not below the threshold, activate at least one inactive section of the volatile memory.   
     
     
         10 . The controller of  claim 2 , wherein the sections of the volatile memory correspond to at least one of a cache line, a memory chip, a memory rank, or a memory bank. 
     
     
         11 . The controller of  claim 2 , further comprising logic to arrange the volatile memory such that read-only pages are located contiguously. 
     
     
         12 . An electronic device, comprising:
 a volatile memory;   a nonvolatile memory; and   a controller comprising logic to:
 determine whether an electronic device comprising a volatile memory and a nonvolatile memory is operating in a low power state; and 
 in response to a determination that the electronic device is operating in the low power state, determine whether a cache miss rate is below a threshold; and
 in response to a determination that the cache miss rate is below the threshold:
 identify one or more sections of the volatile memory that are in a modified state; 
 relocate data only from the one or more sections of the volatile memory that are in the modified state; and 
 power down the one or more sections of the volatile memory. 
 
 
   
     
     
         13 . The device of  claim 12 , wherein relocate data only from the one or more sections of the volatile memory further comprises relocate data only from the one or sections of the volatile memory to a section of the volatile memory. 
     
     
         14 . The device of  claim 12 , wherein relocate data only from the one or more sections of the volatile memory further comprises relocate data only from the one or more sections of the volatile memory to the nonvolatile memory. 
     
     
         15 . The device of  claim 12 , wherein the volatile memory is dynamic random access memory (DRAM). 
     
     
         16 . The device of  claim 12 , wherein the volatile memory is three dimensional ( 3 D) cross point memory. 
     
     
         17 . The device of  claim 12 , wherein the sections of the volatile memory correspond to at least one of a cache line, a memory chip, a memory rank, or a memory bank. 
     
     
         18 . The electronic device of  claim 12 , wherein the controller comprises logic to arrange the volatile memory such that read-only pages are located contiguously. 
     
     
         19 . A method to manage a memory system coupled to an electronic device, comprising:
 determining, in a controller, whether an electronic device comprising a volatile memory and a nonvolatile memory is operating in a low power state; and   in response to determining that the electronic device is operating in the low power state, determining whether a cache miss rate is below a threshold; and   in response to determining that the cache miss rate is below the threshold:
 identifying one or more sections of the volatile memory that are in a modified state; 
 relocating data only from the one or more sections of the volatile memory that are in the modified state; and 
 powering down the one or more sections of the volatile memory. 
   
     
     
         20 . The method of  claim 19 , wherein relocating data only from the one or more sections of the volatile memory further comprises relocating data only from the one or sections of the volatile memory to a section of the volatile memory. 
     
     
         21 . The method of  claim 19 , wherein relocating data only from the one or more sections of the volatile memory further comprises relocating data only from the one or more sections of the volatile memory to the nonvolatile memory. 
     
     
         22 . The method of  claim 19 , further comprising arranging the volatile memory such that read-only pages are located contiguously. 
     
     
         23 . A computer program product comprising logic instructions stored in a non-transitory computer readable medium that, when executed by a controller, configure the controller to perform operations to manage a memory state of a volatile memory, comprising:
 determining whether an electronic device comprising a volatile memory and a nonvolatile memory is operating in a low power state; and   in response to determining that the electronic device is operating in the low power state, determining whether a cache miss rate is below a threshold; and   in response to determining that the cache miss rate is below the threshold:
 identifying one or more sections of the volatile memory that are in a modified state; 
 relocating data only from the one or more sections of the volatile memory that are in the modified state; and 
 powering down the one or more sections of the volatile memory. 
   
     
     
         24 . The computer program product of  claim 23 , wherein relocating data only from the one or more sections of the volatile memory further comprises relocating data only from the one or sections of the volatile memory to a section of the volatile memory. 
     
     
         25 . The computer program product of  claim 23 , wherein relocating data only from the one or more sections of the volatile memory further comprises relocating data only from the one or more sections of the volatile memory to the nonvolatile memory. 
     
     
         26 . The computer program product of  claim 23 , further comprising logic to arrange the volatile memory such that read-only pages are located contiguously.