Transistors with high concentration of boron doped germanium

Abstract

Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm −3 . A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

What is claimed is: 
     
         1 . An integrated circuit transistor, comprising:
 a gate electrode above a channel region, wherein a gate dielectric layer is between the gate electrode and the channel region, and spacers are on sides of the gate electrode;   a source region cavity and a drain region cavity, each of the source cavity and drain cavity adjacent to the channel region, such that the channel region is between the source region cavity and the drain region cavity, each of the source region cavity and the drain region cavity including a tip portion that extends under a corresponding one of the spacers; and   a boron-doped germanium-containing layer in the tip regions, the boron-doped germanium-containing layer having a germanium concentration in excess of 50 atomic % and a boron concentration in excess of 1E20 cm- 3      wherein the integrated circuit transistor is a planar transistor.   
     
     
         2 . The integrated circuit transistor of  claim 1  further comprising:
 a buffer between the channel region and the boron-doped germanium-containing layer, wherein the buffer comprises a layer including silicon and germanium, the layer including silicon and germanium having
 a germanium concentration that is graded from a base level concentration of 40 atomic % or less to a relatively higher level, and/or 
 a boron concentration that is graded to in excess of 1E20 cm −3  from a relatively lower base level concentration. 
 
 
     
     
         3 . The integrated circuit transistor of  claim 2 , wherein the buffer has a thickness between the channel region and the boron-doped germanium-containing layer in the range of 2 nm to 10 nm. 
     
     
         4 . The integrated circuit transistor of  claim 1 , wherein the boron-doped germanium-containing layer comprises:
 a boron-doped silicon germanium (SiGe) portion; and   a boron-doped germanium cap on the boron-doped SiGe portion.   
     
     
         5 . The integrated circuit transistor of  claim 4 , wherein:
 the boron-doped SiGe portion a germanium concentration that is graded from a base level concentration of 40 atomic % or less to a relatively higher level;   the boron-doped SiGe portion has a boron concentration that is graded to in excess of 1E20 cm −3  from a relatively lower base level concentration; and/or   the boron-doped germanium cap has a germanium concentration in excess of 95 atomic %.   
     
     
         6 . The integrated circuit transistor of  claim 4 , wherein the boron-doped SiGe portion has a fixed germanium concentration, and the integrated circuit transistor further comprises a buffer between the boron-doped SiGe portion and the boron-doped germanium cap, the buffer having
 a germanium concentration that is graded from a base level concentration of 40 atomic % or less to a relatively higher level, and   a boron concentration that is graded to in excess of 1E20 cm −3  from a relatively lower base level concentration.   
     
     
         7 . The integrated circuit transistor of  claim 1 , wherein the boron-doped germanium-containing layer has a boron concentration in excess of 5E20 cm −3 . 
     
     
         8 . The integrated circuit transistor of  claim 1 , wherein the integrated circuit transistor is a planar PMOS transistor. 
     
     
         9 . The integrated circuit transistor of  claim 1 , wherein the source and drain cavities are faceted and filled with material that extends above the channel region. 
     
     
         10 . The integrated circuit transistor of  claim 1 , further comprising a source contact and a drain contact, the source and drain contacts including metal-germanide. 
     
     
         11 . An integrated circuit transistor comprising:
 a semiconductor body extending above a substrate, the semiconductor body including a channel region;   a gate structure over the channel region and adjacent multiple surfaces of the semiconductor body, the gate structure including a gate dielectric, a gate electrode, and gate spacers, the gate dielectric being between the gate electrode and the channel region, and the gate spacers being on sides of the gate electrode;   a source region and a drain region, the channel region being between the source region and the drain region, and each of the source region and drain region including a tip region that extends under a corresponding one of the gate spacers; and   a boron-doped germanium-containing layer in the tip regions, the boron-doped germanium-containing layer having a germanium concentration in excess of 50 atomic %, and a boron concentration in excess of 1E20 cm −3 .   
     
     
         12 . The integrated circuit transistor of  claim 11  further comprising:
 a buffer between the semiconductor body and the boron-doped germanium-containing layer, wherein the buffer comprises a layer including silicon and germanium, the layer including silicon and germanium having
 a germanium concentration that is graded from a base level concentration of 40 atomic % or less to a relatively higher level, and/or 
 a boron concentration that is graded to in excess of 1E20 cm −3  from a relatively lower base level concentration. 
 
 
     
     
         13 . The integrated circuit transistor of  claim 12 , wherein the buffer has a thickness between the channel region and the boron-doped germanium-containing layer in the range of 2 nm to 10 nm. 
     
     
         14 . The integrated circuit transistor of  claim 11 , wherein the boron-doped germanium-containing layer comprises:
 a boron-doped silicon germanium (SiGe) portion; and   a boron-doped germanium cap on the boron-doped SiGe portion.   
     
     
         15 . The integrated circuit transistor of  claim 14 , wherein:
 the boron-doped SiGe portion a germanium concentration that is graded from a base level concentration of 40 atomic % or less to a relatively higher level;   the boron-doped SiGe portion has a boron concentration that is graded to in excess of 1E20 cm −3  from a relatively lower base level concentration; and/or   the boron-doped germanium cap has a germanium concentration in excess of 95 atomic %.   
     
     
         16 . The integrated circuit transistor of  claim 14 , wherein the boron-doped SiGe portion has a fixed germanium concentration, and the integrated circuit transistor further comprises a buffer between the boron-doped SiGe portion and the boron-doped germanium cap, the buffer having
 a germanium concentration that is graded from a base level concentration of 40 atomic % or less to a relatively higher level, and   a boron concentration that is graded to in excess of 1E20 cm −3  from a relatively lower base level concentration.   
     
     
         17 . The integrated circuit transistor of  claim 11 , wherein the gate structure is adjacent three surfaces of the semiconductor body to provide a tri-gate transistor configuration. 
     
     
         18 . The integrated circuit transistor of  claim 11 , wherein the integrated circuit transistor is a non-planar PMOS transistor. 
     
     
         19 . The integrated circuit transistor of  claim 11 , wherein the source and drain regions are faceted and filled with material that extends above the channel region. 
     
     
         20 . The integrated circuit transistor of  claim 11 , further comprising a source contact and a drain contact, the source and drain contacts including metal-germanide.