Method for Fabricating a Shallow and Narrow Trench FET

Abstract

According to an embodiment of a method for fabricating a trench field-effect transistor (trench FET), the method includes: forming a trench in a semiconductor substrate of a first conductivity type, the trench including sidewalls which taper from a wider, top portion of the trench to a narrower, bottom portion of the trench; forming a gate dielectric in the trench, the gate dielectric having substantially the same thickness in the wider, top portion of the trench as in the narrower, bottom portion of the trench; forming a gate electrode in the trench and separated from the semiconductor substrate by the gate dielectric; and forming a channel region of a second conductivity type in the semiconductor substrate after forming the trench and the gate dielectric, the channel region being disposed adjacent the trench. Trench FETs formed by the method are also disclosed.

1 - 20 . (canceled) 
     
     
         21 . A method for fabricating a trench field-effect transistor (trench FET), the method comprising:
 forming a trench in a semiconductor substrate of a first conductivity type, the trench including sidewalls which taper from a wider, top portion of the trench to a narrower, bottom portion of the trench;   forming a gate dielectric in the trench, the gate dielectric having substantially the same thickness in the wider, top portion of the trench as in the narrower, bottom portion of the trench;   forming a gate electrode in the trench and separated from the semiconductor substrate by the gate dielectric; and   forming a channel region of a second conductivity type in the semiconductor substrate after forming the trench and the gate dielectric, the channel region being disposed adjacent the trench.   
     
     
         22 . The method of  claim 21 , wherein the channel region is formed by dopant implantation. 
     
     
         23 . The method of  claim 21 , further comprising:
 forming a bottom implanted region of the first conductivity type surrounding the narrower, bottom portion of the trench before forming the gate dielectric in the trench, the bottom implanted region having a dopant concentration greater than the dopant concentration of the semiconductor substrate, the narrower, bottom portion of the trench being disposed in the bottom implanted region.   
     
     
         24 . The method of  claim 21 , wherein the gate electrode is coplanar with a top surface of the semiconductor substrate. 
     
     
         25 . The method of  claim 24 , wherein the gate electrode is made coplanar with a top surface of the semiconductor substrate by chemical mechanical polishing of the top surface. 
     
     
         26 . The method of  claim 21 , further comprising:
 forming a source region of the first conductivity type in the semiconductor substrate adjacent the trench, after forming the trench and the gate dielectric.   
     
     
         27 . The method of  claim 26 , further comprising:
 forming a drift region of the first conductivity type in the semiconductor substrate, the drift region being separated from the source region by the channel region.   
     
     
         28 . The method of  claim 27 , wherein the narrower, bottom portion of the trench is disposed in the drift region. 
     
     
         29 . The method of  claim 26 , further comprising:
 forming a drift region of the first conductivity type in the semiconductor substrate below the channel region so that the source region is separated from the drift region by the channel region; and   forming a bottom implanted region of the first conductivity type surrounding the narrower, bottom portion of the trench before forming the gate dielectric in the trench, the bottom implanted region being disposed in the drift region and having a dopant concentration greater than the dopant concentration of the semiconductor substrate,   wherein the narrower, bottom portion of the trench is disposed in the bottom implanted region.   
     
     
         30 . The method of  claim 26 , wherein the gate electrode is coplanar with a top surface of the source region. 
     
     
         31 . The method of  claim 26 , further comprising:
 forming a recessed region in the semiconductor substrate which extends through the source region and into the channel region,   wherein a top surface of the gate electrode is disposed above a bottom surface of the recessed region.   
     
     
         32 . The method of  claim 26 , wherein a depth of the source region is 0.15 microns or less, wherein a length of the channel region is between 0.3 to 0.45 microns, and wherein a depth of the trench is between 0.6 to 0.8 microns. 
     
     
         33 . The method of  claim 26 , further comprising:
 forming a first dielectric portion over the source region;   forming a second dielectric portion over the trench; and   forming a third dielectric portion over the first and the second dielectric portions.   
     
     
         34 . The method of  claim 33 , further comprising:
 forming a source contact material over the semiconductor substrate,   wherein the second and the third dielectric portions insulate the gate electrode from the source contact material,   wherein the first and the third dielectric portions separate the source contact material from a top surface of the source region,   wherein the source contact material contacts a side face of the source region uncovered by the first and the third dielectric portions.   
     
     
         35 . The method of  claim 21 , wherein the semiconductor substrate is doped to form the channel region after forming the gate electrode. 
     
     
         36 . A trench field-effect transistor (trench FET), comprising:
 a trench formed in a semiconductor substrate of a first conductivity type, the trench including sidewalls which taper from a wider, top portion of the trench to a narrower, bottom portion of the trench;   a gate dielectric formed in the trench, the gate dielectric having substantially the same thickness in the wider, top portion of the trench as in the narrower, bottom portion of the trench;   a gate electrode formed in the trench and separated from the semiconductor substrate by the gate dielectric; and   a channel region of a second conductivity type formed in the semiconductor substrate, the channel region being disposed adjacent the trench.   
     
     
         37 . The trench FET of  claim 36 , further comprising a bottom implanted region of the first conductivity type surrounding the narrower, bottom portion of the trench, wherein the bottom implanted region has a dopant concentration greater than the dopant concentration of the semiconductor substrate, and wherein the narrower, bottom portion of the trench is disposed in the bottom implanted region. 
     
     
         38 . The trench FET of  claim 36 , wherein the gate electrode is coplanar with a top surface of the semiconductor substrate. 
     
     
         39 . The trench FET of  claim 36 , further comprising a source region of the first conductivity type formed in the semiconductor substrate adjacent the trench. 
     
     
         40 . The trench FET of  claim 39 , further comprising a drift region of the first conductivity type formed in the semiconductor substrate, wherein the drift region is separated from the source region by the channel region. 
     
     
         41 . The trench of  claim 40 , wherein the narrower, bottom portion of the trench is disposed in the drift region. 
     
     
         42 . The trench FET of  claim 39 , further comprising:
 a drift region of the first conductivity type formed in the semiconductor substrate below the channel region; and   a bottom implanted region of the first conductivity type surrounding the narrower, bottom portion of the trench,   wherein the source region is separated from the drift region by the channel region,   wherein the bottom implanted region is disposed in the drift region and has a dopant concentration greater than the dopant concentration of the semiconductor substrate,   wherein the narrower, bottom portion of the trench is disposed in the bottom implanted region.   
     
     
         43 . The trench FET of  claim 42 , wherein the gate electrode is coplanar with a top surface of the source region. 
     
     
         44 . The trench FET of  claim 42 , further comprising a recessed region in the semiconductor substrate which extends through the source region and into the channel region, wherein a top surface of the gate electrode is disposed above a bottom surface of the recessed region. 
     
     
         45 . The trench of  claim 42 , wherein a depth of the source region is 0.15 microns or less, wherein a length of the channel region is between 0.3 to 0.45 microns, and wherein a depth of the trench is between 0.6 to 0.8 microns. 
     
     
         46 . The trench FET of  claim 36 , further comprising:
 a first dielectric portion formed over the source region;   a second dielectric portion formed over the trench; and   a third dielectric portion formed over the first and the second dielectric portions.   
     
     
         47 . The trench FET of  claim 46 , further comprising:
 a source contact material formed over the semiconductor substrate,   wherein the second and the third dielectric portions insulate the gate electrode from the source contact material,   wherein the first and the third dielectric portions separate the source contact material from a top surface of the source region,   wherein the source contact material contacts a side face of the source region uncovered by the first and the third dielectric portions.