Processor With Reconfigurable Pipelined Core And Algorithmic Compiler

Abstract

An algorithmic matching pipelined compiler and a reusable algorithmic pipelined core comprise a system. The reusable algorithmic pipelined core is a reconfigurable processing core with a pipelined structure comprising a processor with a setup interface for programming any of a plurality of operations as determined by setup data, a logic decision processor for programming a look up table, a loop counter and a constant register, and a block of memory. This can be used to perform functions. A reconfigurable, programmable circuit routes data and results from one core to another core and/or IO controller and/or interrupt generator, as required to complete an algorithm without further intervention from a central or peripheral processor during processing of an algorithm.

1 . A reusable algorithmic pipelined core, comprising:
 a processing unit;   an array of reconfigurable, field programmable gates, wherein the field programmable gates are programmed by an algorithmic matching pipelined compiler, such that the algorithmic matching pipelined compiler precompiles source code designed for operation on a standard processor without parallel processing for processing by the processing unit, and the processing unit and the algorithmic matching pipelined compiler configures the field programmable gates to operate as pipelined, parallel processors.   
     
     
         2 . The core of  claim 1 , wherein the algorithmic matching pipelined compiler is a precompiler. 
     
     
         3 . The core of  claim 2 , wherein the precompiler is configured to precompile a standard higher level software language written not for the core but for a type of conventional non-reconfigurable processor, and the precompiler generates machine code for the core by utilizing the type of conventional non-reconfigurable processor for which the standard higher level software language was written to generate machine code to configure the array of reconfigurable, field programmable gates. 
     
     
         4 . The core of  claim 3 , wherein the standard higher level software language is C or C++. 
     
     
         5 . The core of  claim 2 , wherein the core comprises a pool of computers configured to process algorithms as needed for a particular calculation, based on output from the precompiler, and
 the field programmable gates are configured to complete tasks without any further overhead from the processing unit.   
     
     
         6 . The core of  claim 5 , further comprising an intelligent bus controller or logical processor, wherein the intelligent bus controller or logical processor performs all of the logical functions processed by the core. 
     
     
         7 . The core of  claim 5 , further comprising a logical processor and a master bus switch, and the logical processor comprises reconfigurable logic functions for controlling of the master bus switch. 
     
     
         8 . The core of  claim 7 , further comprising a digital signal processor, wherein the digital signal processor comprises a reconfigurable mathematical processor for performing mathematical calculations. 
     
     
         9 . The core of  claim 8 , wherein the master bus switch is a matrix bus router or switch comprising a circuit reconfigurably programmable by the precompiler and the processing unit, such that data and results are routed from the core to another core to complete an algorithm, without any further intervention from a central or peripheral processor during the processing of the algorithm, reducing overhead by pipelining compared to static, unreconfigurable hardware, which requires intervention by a central processor or peripheral processor to direct data and results in and out of arithmetic processing units. 
     
     
         10 . The core of  claim 9 , wherein the logical processor processes logical decisions and interative loops and result memory is provided by the logical processor for learning algorithms. 
     
     
         11 . A system comprising a plurality of the cores according to  claim 1 , comprising the steps of:
 processing all of the mathematical operations using digital signal processors of one or more of the plurality of cores; and   processing all of the logic functions using one or more of the logic processors of one or more of the plurality of cores.   
     
     
         12 . The system of  claim 11 , further comprising the step of configuring the plurality of cores as a pool of cores and each of the pool of cores are reconfigurable by programming, alone, without any change to the hardware. 
     
     
         13 . The system of  claim 12 , wherein the step of configuring configures all of the plurality of cores to process algorithms in parallel without any further intervention from a central or peripheral processor to direct data and results in an out of arithmetic processing units. 
     
     
         14 . The system of  claim 13 , wherein the algorithmic matching pipelined compiler is a precompiler, and the logic processor of each of the plurality of cores uses memory blocks configured by the precompiler, as look up tables and registers for constants or learned values. 
     
     
         15 . The system of  claim 14 , further comprising setting up the look up table by the logic processor, wherein the look up table is an n-bit look up table, and the n-bit look up table is used to encode an n-bit Boolean logic function as truth tables. 
     
     
         16 . The system of  claim 11 , further comprising: generating machine code from a standard higher level software language written for a conventional, non-reconfigurable and non-pipelined, general purpose computer processor, using the algorithmic matching pipelined compiler for one or more of the plurality of cores. 
     
     
         17 . The system of  claim 16 , wherein the standard higher level software language is written for a type of conventional, non-reconfigurable processor, and the step of generating machine code comprises the algorithmic matching pipelined compiler, as a precompiler, utilizing the type of conventional, non-reconfigurable processor to generate machine code for configuring the array of reconfigurable, field programmable gates of each of the plurality of cores. 
     
     
         18 . The system of  claim 17 , wherein the system comprises at least one processor of the type of conventional, non-reconfigurable processor for which the standard higher level software language is written, and the at least one processor of the type of conventional, non-reconfigurable processor for which the standard higher level software language is written is generates the machine code for configuring the array of reconfigurable, field programmable gates of each of the plurality of cores. 
     
     
         19 . The system of  claim 18 , wherein each of the plurality of cores is configured to independently solve complex mathematical and logic algorithms without further intervention by the at least one processor of the type of conventional, non-reconfigurable processor for which the standard higher level software language is written. 
     
     
         20 . The system of  claim 19 , further comprising inputting values into the system, and the system outputs a solution to a master bus switch of the system, without further intervention. 
     
     
         21 . The system of  claim 20 , wherein the plurality of cores comprises 2000 cores. 
     
     
         22 . The system of  claim 21 , wherein the system operates 360 trillion instructions per second with a 500 MHz clock speed. 
     
     
         23 . The system of  claim 22 , wherein the system has a latency for input of data, but pipelining reduces overhead such that the system is configured to execute a calculation and output a result on each clock from each core after the latency is initiated.