Tft substrate and method for manufacturing the same

Abstract

A TFT substrate and a method for manufacturing the TFT substrate are provided. A TFT structure is formed on a substrate. A color resist layer is formed on the substrate, and a first opening area is formed in the color resist layer at a location corresponding to the TFT structure. A first black matrix is formed in the first opening area such that the TFT structure is covered by the first black matrix. A pixel electrode is formed on the color resist layer and the first black matrix and is electrically coupled to the TFT structure through the first black matrix. With such an arrangement, light can be shielded and light transmittance can be reduced when a panel including the TFT substrate is bent. This helps improve contrast of the panel.

What is claimed is: 
     
         1 . A thin film transistor (TFT) substrate, comprising:
 a substrate;   a TFT structure, which is disposed above the substrate;   a color resist layer, which is disposed above the substrate, wherein a first opening area in the color resist layer is formed at a location corresponding to the TFT structure;   a first black matrix, which is disposed in the first opening area such that the TFT structure is covered by the first black matrix; and   a pixel electrode, which is disposed above the color resist layer and the first black matrix and is electrically coupled to the TFT structure through the first black matrix.   
     
     
         2 . The TFT substrate according to  claim 1  further comprising:
 an electrode capacitor, which is disposed above the substrate, wherein a second opening area is formed in the color resist layer at a location corresponding to the electrode capacitor; and 
 a second black matrix, which is disposed in the second opening area such that the electrode capacitor is covered by the second black matrix. 
 
     
     
         3 . The TFT substrate according to  claim 2 , wherein the electrode capacitor comprises a first capacitor electrode and a second capacitor electrode;
 wherein a gate electrode is disposed above the substrate;   a scan line and the first capacitor electrode are disposed on a layer that is the same as the gate electrode;   a first insulating layer and an active layer are sequentially disposed above the gate electrode, wherein the scan line and the first capacitor electrode are further covered by the first insulating layer and the scan line and the first capacitor electrode are not covered by the active layer;   a source electrode and a drain electrode re disposed above the active layer;   the second capacitor electrode is disposed above the first capacitor electrode and is on a layer that is the same layer the same as the source electrode and the drain electrode; and   a second insulating layer is disposed above the source electrode, the drain electrode, and the second capacitor electrode, wherein the color resist layer, the first black matrix, and the second black matrix are formed above the second insulating layer; and the pixel electrode is electrically coupled to one of the source electrode and the drain electrode through the first black matrix and the second insulating layer and is further electrically coupled to the second capacitor electrode through the second black matrix and the second insulating layer.   
     
     
         4 . The TFT substrate according to  claim 3  further comprising:
 an insulating protection layer, which is disposed between the pixel electrode and the first black matrix, the second black matrix, and the color resist layer. 
 
     
     
         5 . The TFT substrate according to  claim 4 , wherein a first contact hole is formed in the first black matrix and the second insulating layer at a location corresponding to one of the source electrode and the drain electrode, and a second contact hole is formed in the second black matrix and the second insulating layer at a location corresponding to the second capacitor electrode;
 the insulating layer is formed in the first contact hole and the second contact hole; and   a third contact hole and a fourth contact hole are formed in the insulating protection layer in the first contact hole and the second contact hole, respectively, wherein the pixel electrode is electrically coupled to one of the source electrode and the drain electrode through the third contact hole and is electrically coupled to the second capacitor electrode through the fourth contact hole.