Integrated circuit and process thereof

Abstract

An integrated circuit process includes the following steps. A substrate including a flash cell area and a logic area is provided. A first sacrificial gate on the substrate of the flash cell area and a second sacrificial gate on the substrate of the logic area are formed, and a dielectric layer covers the substrate beside the first sacrificial gate and the second sacrificial gate. The first sacrificial gate is removed to forma first recess in the dielectric layer. An oxide/nitride/oxide layer is formed to conformally cover surfaces of the first recess. An integrated circuit formed by said integrated circuit process is also provided.

1 . An integrated circuit process, comprising:
 providing a substrate comprising a flash cell area and a logic area;   forming a first sacrificial gate on the substrate of the flash cell area and a second sacrificial gate on the substrate of the logic area, and covering the substrate beside the first sacrificial gate and the second sacrificial gate with a dielectric layer;   removing the first sacrificial gate to form a first recess in the dielectric layer; and   forming an oxide/nitride/oxide layer to conformally cover surfaces of the first recess, wherein the oxide/nitride/oxide layer is only in the flash cell area.   
     
     
         2 . The integrated circuit process according to  claim 1 , wherein the step of removing the first sacrificial gate comprises:
 covering a patterned first mask on the second sacrificial gate and then removing the first sacrificial gate.   
     
     
         3 . The integrated circuit process according to  claim 1 , further comprising:
 forming a first metal gate in the first recess after the oxide/nitride/oxide layer is formed.   
     
     
         4 . The integrated circuit process according to  claim 1 , further comprising:
 forming a first dielectric layer below the first sacrificial gate and a second dielectric layer below the second sacrificial gate after providing the substrate.   
     
     
         5 . The integrated circuit process according to  claim 1 , wherein the first dielectric layer and the second dielectric layer comprise dielectric layers having a high dielectric constant. 
     
     
         6 . The integrated circuit process according to  claim 5 , wherein the first dielectric layer is removed while the first sacrificial gate is removed. 
     
     
         7 . The integrated circuit process according to  claim 1 , further comprising:
 removing the second sacrificial gate to form a second recess in the dielectric layer after the oxide/nitride/oxide layer is formed; and   forming a second metal gate in the second recess and a first metal gate in the first recess at the same time.   
     
     
         8 . The integrated circuit process according to  claim 7 , wherein the step of forming the first metal gate and the second metal gate comprises:
 sequentially covering a work function metal layer, a barrier layer and a main conductive layer in the first recess, the second recess and the dielectric layer; and   planarizing the main conductive layer, the barrier layer and the work function metal layer to form the first metal gate and the second metal gate.   
     
     
         9 . The integrated circuit process according to  claim 7 , wherein the step of removing the second sacrificial gate comprises:
 covering a patterned second mask on the substrate of the flash cell area and then removing the second sacrificial gate.   
     
     
         10 . The integrated circuit process according to  claim 7 , wherein the dimension of the first recess is larger than the dimension of the second recess. 
     
     
         11 . The integrated circuit process according to  claim 1 , further comprising:
 forming a first dielectric layer below the first sacrificial gate and a second dielectric layer below the second sacrificial gate after providing the substrate.   
     
     
         12 . The integrated circuit process according to  claim 11 , wherein the second dielectric layer is reserved while the second sacrificial gate is removed. 
     
     
         13 . The integrated circuit process according to  claim 11 , wherein the oxide/nitride/oxide layer has a bottom surface trimmed with a bottom surface of the second dielectric layer. 
     
     
         14 . The integrated circuit process according to  claim 1 , further comprising:
 forming a contact etch stop layer on the substrate, the first sacrificial gate and the second sacrificial gate;   forming the dielectric layer on the contact etch stop layer; and   planarizing the contact etch stop layer and the dielectric layer.   
     
     
         15 . An integrated circuit, comprising:
 a substrate comprising a flash cell area and a logic area;   a first gate disposed on the substrate of the flash cell area and a second gate disposed on the substrate of the logic area; and   an oxide/nitride/oxide layer disposed below the first gate while a dielectric layer having a high dielectric constant is disposed below the second gate.   
     
     
         16 . The integrated circuit according to  claim 15 , wherein the oxide/nitride/oxide layer has a bottom surface trimmed with a bottom surface of the dielectric layer having a high dielectric constant. 
     
     
         17 . The integrated circuit according to  claim 15 , wherein the first gate comprises a first metal gate, and the oxide/nitride/oxide layer is sandwiched by the first metal gate and the substrate, while the second gate comprises a second metal gate, and the dielectric layer having a high dielectric constant is sandwiched by the second metal gate and the substrate. 
     
     
         18 . The integrated circuit according to  claim 17 , wherein the first metal gate is the same as the second metal gate. 
     
     
         19 . The integrated circuit according to  claim 15 , further comprising:
 a dielectric layer covering the substrate, wherein the first gate is disposed in a first recess of the dielectric layer while the second gate is disposed in a second recess of the dielectric layer.   
     
     
         20 . The integrated circuit according to  claim 19 , wherein the dimension of the first recess is larger than the dimension of the second recess.