Semiconductor image sensor module and method of manufacturing the same

Abstract

A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.

1 . An imaging device, comprising:
 a first semiconductor chip including:
 a plurality of pixels arranged in a first array, respective ones of the pixels including a photoelectric conversion element disposed at a light incident side of the first semiconductor chip, and 
 a multilayer wiring layer disposed below the photoelectric conversion element and disposed at a side opposite the light incident side; and 
   a second semiconductor chip including a first circuit, wherein   an area of the first semiconductor chip is comparable to an area of the second semiconductor chip,   the first semiconductor chip is stacked over the second semiconductor chip such that the side opposite the light incident side of the first semiconductor chip faces a surface of the second semiconductor chip, and   the first semiconductor chip and the second semiconductor chip are connected to one another via at least one of a plurality of connection portions.   
     
     
         2 . The imaging device according to  claim 1 , wherein the plurality of connection portions are disposed from the multilayer wiring layer to the second semiconductor chip through the side opposite the light incident side of the first semiconductor chip. 
     
     
         3 . The imaging device according to  claim 1 , wherein the first circuit includes a plurality of analog to digital converters arranged in a second array. 
     
     
         4 . The imaging device according to  claim 3 , wherein the plurality of pixels are grouped in a plurality of pixel array units, and wherein a respective analog to digital converter corresponds to a corresponding pixel array unit. 
     
     
         5 . The imaging device according to  claim 3 , wherein the plurality of pixels are configured to output a respective analog signal, and wherein a respective analog to digital converter is configured to receive a corresponding analog signal via at least one of the plurality of connection portions. 
     
     
         6 . The imaging device according to  claim 3 , wherein the plurality of analog to digital converters respectively include a comparator and a counter. 
     
     
         7 . The imaging device according to  claim 1 , wherein the first semiconductor chip includes a transistor region including transistors corresponding to each of the photoelectric conversion elements, and a photodiode region including the respective photoelectric conversion elements. 
     
     
         8 . The imaging device according to  claim 1 , wherein the plurality of connection portions includes first pads formed at the side opposite the light incident side of the first semiconductor chip and second pads formed at the surface of the second semiconductor chip, and wherein a respective first pad positionally corresponds to a corresponding second pad. 
     
     
         9 . The imaging device according to  claim 1 , wherein the side opposite the light incident side of the first semiconductor chip is bonded to the surface of the second semiconductor chip with an adhesive material. 
     
     
         10 . The imaging device according to  claim 1 , wherein the first semiconductor chip includes a first connection portion of the plurality of connection portions, and the second semiconductor chip includes a second connection portion of the plurality of connection portions. 
     
     
         11 . The imaging device according to  claim 10 , wherein the first connection portion is a first pad, and the second connection portion is a second pad. 
     
     
         12 . The imaging device according to  claim 1 , further comprising a third semiconductor chip including a second circuit, wherein the second semiconductor chip is stacked over the third semiconductor chip. 
     
     
         13 . The imaging device according to  claim 12 , wherein the second circuit includes a plurality of memory elements. 
     
     
         14 . The imaging device according to  claim 13 , wherein the plurality of memory elements are volatile memories. 
     
     
         15 . The imaging device according to  claim 1 , wherein respective ones of the pixels include a transfer transistor, a reset transistor, an amplifier transistor, and a select transistor. 
     
     
         16 . The imaging device according to  claim 1 , wherein adjacent ones of the pixels share a reset transistor, an amplifier transistor, and a select transistor. 
     
     
         17 . The imaging device according to  claim 1 , wherein the first semiconductor chip includes a driver circuit configured to drive the plurality of pixels, the driver circuit being adjacent to the first array. 
     
     
         18 . The imaging device according to  claim 1 , wherein the first semiconductor chip includes a plurality of signal lines. 
     
     
         19 . The imaging device according to  claim 1 , wherein the photoelectric conversion element is a photodiode. 
     
     
         20 . The imaging device according to  claim 1 , wherein the photoelectric conversion element is a plurality of photodiodes.