Method and apparatus for preventing non-temporal entries from polluting small structures using a transient buffer

Abstract

A method for preventing non-temporal entries from entering small critical structures is disclosed. The method comprises transferring a first entry from a higher level memory structure to an intermediate buffer. It further comprises determining a second entry to be evicted from the intermediate buffer and a corresponding value associated with the second entry. Subsequently, responsive to a determination that the second entry is frequently accessed, the method comprises installing the second entry into a lower level memory structure. Finally, the method comprises installing the first entry into a slot previously occupied by the second entry in the intermediate buffer.

1 . A method for preventing non-temporal entries from entering small critical structures, said method comprising:
 receiving data from a higher level memory structure at an intermediate buffer, the higher level memory structure having a higher latency relative to a processor than the intermediate buffer;   determining an entry to be evicted from the intermediate buffer that has been frequently accessed;   sending a value in the determined entry to a lower level memory structure, the lower level memory structure having a lower latency relative to the processor than the intermediate buffer; and   storing the data in the determined entry of the intermediate buffer.   
     
     
         2 . The method of  claim 1 , wherein the higher level memory structure is a Level 2 cache memory. 
     
     
         3 . The method of  claim 1 , wherein the lower level memory structure is any one of a L1 data cache memory, a L1 instruction cache memory and a conversion lookaside buffer. 
     
     
         4 . The method of  claim 1 , further comprising:
 receiving an access request for the entry in the intermediate buffer; and   increasing an access counter for the entry.   
     
     
         5 . The method of  claim 4 , further comprising:
 comparing the access counter to a threshold to move the entry to the lower level memory structure.   
     
     
         6 . The method of  claim 1 , wherein the determining is based on a replacement policy, wherein the replacement policy is any one of an access counter based replacement policy, a least-recently used replacement policy and a random replacement policy. 
     
     
         7 . The method of  claim 1 , further comprising:
 discarding another entry in the intermediate buffer where an access count of the other entry is below a discard threshold.   
     
     
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         15 . An apparatus for preventing non-temporal entries from entering small critical structures, said apparatus comprising:
 a memory;   a processor communicatively coupled to the memory;   a low level memory structure coupled to the processor, the low level memory structure with a lower latency to the processor than the memory; and   an intermediate buffer coupled to the low level memory structure, the intermediate buffer having a latency that is lower than the memory, the intermediate buffer to receive a first block from the memory, the intermediate buffer having replacement logic to determine an entry to be evicted from the intermediate buffer that has been frequently accessed, to send a second block in the determined entry to the lower level memory structure, and to store the first block in the determined entry of the intermediate buffer.   
     
     
         16 . The apparatus of  claim 15 , further comprising:
 Level 2 cache memory having a latency that is higher than the intermediate buffer and lower than the memory.   
     
     
         17 . The apparatus of  claim 15 , wherein the lower level memory structure is any one of a L1 data cache memory, a L1 instruction cache memory and a conversion lookaside buffer. 
     
     
         18 . The apparatus of  claim 15 , wherein said the intermediate buffer includes confidence logic to discard the second block responsive to a determination that the second block is not frequently accessed. 
     
     
         19 . The apparatus of  claim 18 , wherein the confidence logic compares an access counter of the second block to a threshold to move the second block to the lower level memory structure. 
     
     
         20 . The apparatus of  claim 15 , wherein the replacement logic is configured to determine the second block to be evicted based on a replacement policy, wherein the replacement policy is any one of an access counter based replacement policy, a least-recently used replacement policy and a random replacement policy. 
     
     
         21 . The method of  claim 1 , further comprising:
 receiving a fetch at the intermediate buffer simultaneous to the fetch being processed at the lower level memory structure.   
     
     
         22 . The method of  claim 1 , further comprising:
 sending an entry to the lower level memory structure in response to an access causing an access count to exceed a move threshold.   
     
     
         23 . The apparatus of  claim 15 , wherein the processor sends a fetch to the intermediate buffer simultaneous to the fetch being sent to the lower level memory structure. 
     
     
         24 . The apparatus of  claim 15 , wherein the replacement logic and confidence logic are configured to send a third block to the lower level memory structure in response to an access of the third block causing an access count to exceed a move threshold.