US2017186772A1PendingUtilityA1

Semiconductor Chip Including Integrated Circuit Defined Within Dynamic Array Section

Assignee: TELA INNOVATIONS INCPriority: Mar 7, 2007Filed: Mar 13, 2017Published: Jun 29, 2017
Est. expiryMar 7, 2027(~0.6 yrs left)· nominal 20-yr term from priority
H10W 20/43H10W 20/42G06F 30/39G06F 2119/18H01L 2027/11874H01L 23/528H01L 23/5226G06F 17/5068H01L 2027/11866H01L 27/0207G06F 2217/12H01L 2027/1182H01L 2027/11888H01L 27/11807H10D 84/988H10D 84/974H10D 84/966H10D 84/921H10D 89/10H10D 84/903H10D 84/907Y02P90/02
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Claims

Abstract

A semiconductor chip includes four linear-shaped conductive structures that each form a gate electrode of corresponding transistor of a first transistor type and a gate electrode of a corresponding transistor of a second transistor type. First and second ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines separated by a gate electrode pitch. Third and fourth ones of the four linear-shaped conductive structures are also positioned to have their lengthwise-oriented centerlines separated by the gate electrode pitch. The first and third ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines co-aligned and are separated by a first end-to-end spacing. The second and fourth ones of the four linear-shaped conductive structures are positioned to have their lengthwise-oriented centerlines co-aligned and are separated by a second end-to-end spacing substantially equal in size to the first end-to-end spacing.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor chip, comprising:
 a region including at least nine gate electrode tracks, the at least nine gate electrode tracks positioned such that a distance as measured perpendicular to the at least nine gate electrode tracks and between any two of the at least nine gate electrode tracks is substantially equal to an integer multiple of a gate electrode pitch,   each of the at least nine gate electrode tracks including one or more conductive segments,   the conductive segments of the at least nine gate electrode tracks including a first conductive segment that forms a gate electrode of a first transistor of a first transistor type,   the conductive segments of the at least nine gate electrode tracks including a second conductive segment that forms a gate electrode of a first transistor of a second transistor type,   the conductive segments of the at least nine gate electrode tracks including a third conductive segment that forms a gate electrode of a second transistor of the first transistor type,   the conductive segments of the at least nine gate electrode tracks including a fourth conductive segment that forms a gate electrode of a second transistor of the second transistor type,   the conductive segments of the at least nine gate electrode tracks including a fifth conductive segment that forms a gate electrode of a third transistor of the first transistor type,   the conductive segments of the at least nine gate electrode tracks including a sixth conductive segment that forms a gate electrode of a third transistor of the second transistor type,   the conductive segments of the at least nine gate electrode tracks including a seventh conductive segment that forms a gate electrode of a fourth transistor of the first transistor type,   the conductive segments of the at least nine gate electrode tracks including an eighth conductive segment that forms a gate electrode of a fourth transistor of the second transistor type,   the first and third conductive segments separated by a center-to-center distance as measured perpendicular to the at least nine gate electrode tracks substantially equal to the gate electrode pitch,   the fourth and sixth conductive segments separated by a center-to-center distance as measured perpendicular to the at least nine gate electrode tracks substantially equal to the gate electrode pitch.

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