3-dimensional semiconductor memory device and operating method thereof

Abstract

Disclosed is a three-dimensional semiconductor memory device, comprising a cell array formed on a first substrate and a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, wherein the peripheral circuit is configured to provide signals for controlling the cell array. The cell array comprises insulating patterns and gate patterns stacked alternately on the first substrate, and at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns. The three-dimensional semiconductor memory device further comprising a first ground selection transistor that includes a first gate pattern, adjacent to the first substrate and the first pillar, and a second ground selection transistor that includes a second gate pattern positioned on the first gate pattern and the first pillar, and wherein the first ground selection transistor is not programmable, and the second ground selection transistor is programmable.

1 . A three-dimensional semiconductor memory device comprising:
 a cell array formed on a first substrate; and   a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, the peripheral circuit being configured to provide signals for controlling the cell array,   wherein the cell array comprises:   insulating patterns and gate patterns stacked alternately on the first substrate; and   at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns,   wherein a first ground selection transistor includes a first gate pattern, adjacent to the first substrate and the first pillar, and a second ground selection transistor includes a second gate pattern positioned on the first gate pattern and the first pillar, and   wherein the first ground selection transistor is not programmable, and the second ground selection transistor is programmable.   
     
     
         2 .- 23 . (canceled)