System and method for providing 3d wafer assembly with known-good-dies
Abstract
Systems and methods for providing 3D wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. Defective dies on multiple wafers may be removed in parallel, and resulting wafers with all good dies stacked in 3D wafer assembly. In an implementation, the spaces left by removed defective dies may be filled at least in part with operational dies or with a fill material. Defective dies may be replaced either before or after wafer-to-wafer assembly to eliminate production of defective stacked devices, or the spaces may be left empty. A bottom device wafer may also have its defective dies removed or replaced, resulting in wafer-to-wafer assembly that provides 3D stacks with no defective dies.
Claims
exact text as granted — not AI-modified1 . A method, comprising:
compiling an index of good dies or an index of defective dies on a wafer of a semiconductor material, the wafer composed of a plurality of dies; utilizing the wafer in a wafer-to-wafer (W2W) assembly of stacked devices; and individually replacing each of the defective dies with a known-good-die according to the index either before or after the W2W assembly to eliminate production of defective stacked devices.
2 . The method of claim 1 , further comprising:
excising the defective dies from the wafer according to the index, resulting in empty sites on the wafer; bonding the wafer to a second wafer of a semiconductor material; and individually bonding a known-good-die to the second wafer at each empty site of the wafer to fill in the empty sites of the wafer.
3 . The method of claim 2 , further comprising:
before bonding the wafer to the second wafer, bonding the second wafer to a carrier; individually replacing each defective die in the second wafer; and removing the carrier after bonding the wafer to the second wafer.
4 . The method of claim 1 , wherein individually replacing each of the defective dies further comprises laser dicing or plasma etching each defective die from the respective wafer.
5 . The method of claim 1 , further comprising:
backgrinding the wafer to reduce a wafer thickness; removing the defective dies by laser full-cut dicing or plasma etching, leaving empty sites in the wafer; bonding a front side of the wafer to a bottom device wafer; and individually bonding a known-good-die to the bottom device wafer at each empty site in the wafer.
6 . The method of claim 5 , further comprising individually bonding the known-good-die to the bottom device wafer at each empty site in the wafer using a pick-and-place bonding operation.
7 . The method of claim 5 , further comprising a direct bond interconnect (DBI) operation in the W2W assembly.
8 . The method of claim 7 , further comprising annealing bonds formed in the W2W assembly.
9 . The method of claim 5 , further comprising:
thinning a backside of the wafer; depositing an oxide to fill grooves on the wafer; and polygrinding the backside to reveal through-silicon-vias (TSVs).
10 . The method of claim 9 , further comprising;
depositing an oxide layer; applying a chemical-mechanical planarization (CMP) to the wafer; applying one or more back-end-of-line operations to the wafer; applying one or more DBI layers to the wafer; and bonding more wafers or more layers to the wafer.
11 . The method of claim 1 , further comprising:
backgrinding the wafer to reduce a wafer thickness; removing the defective dies by laser full-cut dicing or plasma etching, leaving empty sites in the wafer; mounting a front side of the wafer on a temporary carrier; individually bonding a known-good-die to the temporary carrier at each empty site in the wafer; filling gaps around the replaced known-good-dies with a molding material, an oxide, or a BCB material.
12 . The method of claim 12 , further comprising:
performing one or more W2W bonding operations; and debonding the temporary carrier.
13 . The method of claim 1 , further comprising:
disabling the defective dies before the W2W assembly by laser ablation or etching a thin layer of the wafer at the site of each defective die; bonding a front side of the wafer to a bottom device wafer; backgrinding a backside of the wafer, but not exposing TSVs; applying a laser partial cut or a plasma etching to remove the defective dies, leaving corresponding empty sites; and bonding a known-good-die at each empty site.
14 . The method of claim 13 , further comprising:
depositing an oxide or a CMP-compatible material to fill vertical grooves on the wafer; thinning a backside of the wafer, and polygrinding to reveal the TSVs.
15 . The method of claim 14 , further comprising stacking multiple layers of wafers using the previous steps for parallel manufacturing.
16 . An apparatus, comprising:
a first wafer of a semiconductor material; a second wafer or carrier; a wafer-to-wafer (W2W) bond between the second wafer or carrier and known-good-dies of the first wafer; and a die-to-wafer (D2W) bond between the second wafer or carrier and each replaced die of the first wafer, each bad die of the first wafer replaced with a known-good-die.
17 . The apparatus of claim 16 , further comprising:
a stack comprising at least the first wafer bonded to one or more additional wafers; and a known-good-die replacing each bad die in the first wafer and in each of the one or more additional wafers.
18 . The apparatus of claim 16 , wherein the W2W bond comprises a DBI bond.
19 . A method, comprising:
forming a wafer-to-wafer (W2W) bond between good dies of a wafer and a second wafer or carrier; and forming a die-to-wafer (D2W) bond between each replacement die of the wafer and the second wafer or carrier.
20 . The method of claim 19 , further comprising:
forming the W2W bond between the wafer and the second wafer or carrier, wherein the wafer has empty sites where bad dies have been removed; and forming the D2W bond at each empty site.Join the waitlist — get patent alerts
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