Mode-specific endbranch for control flow termination

Abstract

A processor includes an execution unit and a processing logic operatively coupled to the execution unit, the processing logic to: enter a first execution state and transition to a second execution state responsive to executing a control transfer instruction. Responsive to executing a target instruction of the control transfer instruction, the processing logic further transitions to the first execution state responsive to the target instruction being a control transfer termination instruction of a mode identical to a mode of the processing logic following the execution of the control transfer instruction; and raises an execution exception responsive to the target instruction being a control transfer termination instruction of a mode different than the mode of the processing logic following the execution of the control transfer instruction.

What is claimed is: 
     
         1 . A processor comprising:
 an execution unit; and   a processing logic operatively coupled to the execution unit, the processing logic to:
 enter a first execution state; 
 transition to a second execution state responsive to executing a control transfer instruction; 
 responsive to executing a target instruction of the control transfer instruction:
 transition to the first execution state responsive to the target instruction being a control transfer termination instruction of a mode identical to a mode of the processing logic following the execution of the control transfer instruction; and 
 raise an execution exception responsive to the target instruction being a control transfer termination instruction of a mode different than the mode of the processing logic following the execution of the control transfer instruction. 
 
   
     
     
         2 . The processor of  claim 1 , wherein the target instruction is a 32-bit instruction and the mode of the processing logic following the control transfer instruction is 64-bit. 
     
     
         3 . The processor of  claim 1 , wherein the target instruction is a 64-bit instruction and the mode of the processing logic following the control transfer instruction is 32-bit. 
     
     
         4 . The processor of  claim 1 , wherein the control transfer instruction is an indirect call or jump instruction and the control transfer termination instruction is an ENDBRANCH instruction. 
     
     
         5 . The processor of  claim 1 , wherein the control transfer instruction is a return instruction and the control transfer termination instruction is an ENDRET instruction. 
     
     
         6 . The processor of  claim 1 , wherein the control transfer termination instruction is a mode-specific, multi-byte opcode executable as a no operation. 
     
     
         7 . The processor of  claim 1 , wherein the first execution state comprises an IDLE state and wherein the second execution state comprises a WAIT state. 
     
     
         8 . A processor comprising a decode unit to decode instructions according to a first mode or a second mode depending on a mode of the instructions, wherein the decode unit includes a processing logic to raise an execution exception responsive to a next instruction, decoded after a control transfer instruction, being a control transfer termination instruction of the second mode when the mode of the processing logic following the execution of the control transfer instruction is of the first mode, wherein the control transfer termination instruction is a mode-specific, multi-byte opcode executable as a no operation. 
     
     
         9 . The processor of  claim 8 , wherein the first mode is 32-bit the second mode is 64-bit. 
     
     
         10 . The processor of  claim 8 , wherein the first mode is 64-bit the second mode is 32-bit. 
     
     
         11 . The processor of  claim 8 , wherein the control transfer instruction is an indirect call or jump instruction and the control transfer termination instruction is an ENDBRANCH instruction. 
     
     
         12 . The processor of  claim 8 , wherein the control transfer instruction is a return instruction and the control transfer termination instruction is an ENDRET instruction. 
     
     
         13 . The processor of  claim 8 , further comprising an execution pipeline, wherein the decode unit is further to:
 decode the control transfer instruction into a micro-operation;   generate a fault micro-operation responsive to detecting a conflict in mode between the control transfer termination instruction and the mode of the processing logic following execution of the control transfer instruction; and   feed the micro-operation and the fault micro-operation into the execution pipeline.   
     
     
         14 . A system comprising:
 a fetch unit to fetch instructions of a first mode and a second mode;   a decode unit to decode the instructions, the decode unit further to, responsive to a control transfer instruction, decode the control transfer instruction into a first micro-operation;   an execution unit operatively coupled to the decode unit and to execute micro-operations from decoded instructions; and   a retirement unit to retire the first micro-operation, the retirement unit including processing logic to raise an execution exception when a next micro-instruction to be retired after the first micro-operation is a control transfer termination micro-instruction of the second mode when the mode of the processing logic following execution of the first micro-operation is of the first mode.   
     
     
         15 . The system of  claim 14 , wherein the control transfer termination micro-instruction is generated from a mode-specific, multi-byte opcode executable as a no operation. 
     
     
         16 . The system of  claim 14 , wherein the first mode is 32-bit the second mode is 64-bit. 
     
     
         17 . The system of  claim 14 , wherein the first mode is 64-bit the second mode is 32-bit. 
     
     
         18 . The system of  claim 14 , wherein the processing logic is further to associate a first state with the first micro-operation decoded from the control transfer instruction to indicate that the processing logic is in a WAIT state. 
     
     
         19 . The system of  claim 18 , wherein the decode unit is further to associate a second state with a second micro-operation decoded from a second control transfer instruction that is followed by a control transfer termination instruction of the same mode as the mode of the processing logic following execution of second control transfer instruction, wherein the second state is to indicate that the processing logic is in an IDLE state. 
     
     
         20 . The system of  claim 14 , wherein the retirement unit is further to communicate a last retired micro-instruction and a last state of the processing logic associated with the last retired micro-instruction to the decode unit responsive to a misprediction, and wherein the decode unit is further to update a state of the processing logic in view of the last state.