Phase locked loop and associated method for loop gain calibration

Abstract

A phase locked loop (PLL) includes a controllable oscillator, a charge pump, a type II loop filter, a frequency divider, a phase error processing circuit, a phase frequency detector and a phase alignment circuit. The controllable oscillator generates an oscillating signal. The charge pump circuit generates a charge pump output in a calibration mode. The type II loop filter generates a first control signal to the controllable oscillator according to the charge pump output. The frequency divider performs frequency division upon the oscillating signal for generating a feedback signal. The phase error processing circuit outputs an adjusting signal by comparing a reference signal with the feedback signal. The phase frequency detector generates a detection signal by comparing the feedback signal and the reference signal. The phase alignment circuit generates a second control signal in the calibration mode.

What is claimed is: 
     
         1 . A phase locked loop, comprising:
 a controllable oscillator, arranged to generate an oscillating signal;   a charge pump circuit, arranged to receive a calibration signal and generate a charge pump output according to the calibration signal when the PLL operates in a calibration mode;   a type II loop filter, arranged to receive the charge pump output, and generate a first control signal to the controllable oscillator according to the charge pump output;   a frequency divider, arranged to receive the oscillating signal outputted from the controllable oscillator and an adjusting signal, and refer to the adjusting signal to perform frequency division upon the oscillating signal for generating a feedback signal;   a phase error processing circuit, arranged to receive the feedback signal and a reference signal, and output the adjusting signal based on a comparison result of the reference signal and the feedback signal;   a phase frequency detector, arranged to receive the feedback signal and the reference signal, and compare the feedback signal and the reference signal to generate a detection signal; and   a phase alignment circuit, arranged to receive the detection signal, and generate a second control signal to the controllable oscillator according to the detection signal when the PLL operates in the calibration mode.   
     
     
         2 . The PLL of  claim 1 , wherein the phase alignment circuit comprises:
 an auxiliary charge pump circuit, arranged to receive the detection signal and generate an auxiliary charge pump output according to the detection signal; and   an auxiliary loop filter, arranged to receive the auxiliary charge pump output and generate the second control signal to the controllable oscillator according to the auxiliary charge pump output.   
     
     
         3 . The PLL of  claim 2 , wherein the auxiliary loop filter is a type I loop filter. 
     
     
         4 . The PLL of  claim 1 , wherein when the PLL operates in a normal operation mode, the phase alignment circuit is disabled. 
     
     
         5 . The PLL of  claim 1 , further comprising:
 a multiplexer, having a first input port, a second input port, and an output port, wherein the first input port is arranged to receive the detection signal, the second input port is arranged to receive the calibration signal, and the output port is arranged to output the detection signal to the charge pump circuit when the PLL operates in a normal operation mode, and output the calibration signal to the charge pump circuit when the PLL operates in the calibration mode.   
     
     
         6 . A method for controlling a phase locked loop (PLL), comprising:
 configuring a controllable oscillator to generate an oscillating signal;   generating a charge pump output of a charge pump circuit according to a calibration signal when the PLL operates in a calibration mode;   configuring a type II loop filter to receive the charge pump output, and generate a first control signal to the controllable oscillator according to the charge pump output;   referring to an adjusting signal to perform frequency division upon the oscillating signal for generating a feedback signal;   modifying the adjusting signal based on a comparison result of a reference signal and the feedback signal;   comparing the feedback signal and the reference signal to generate a detection signal; and   generating a second control signal to the controllable oscillator according to the detection signal when the PLL operates in the calibration mode.   
     
     
         7 . The method of  claim 6 , wherein the phase alignment circuit comprises:
 an auxiliary charge pump circuit, arranged to receive the detection signal and generate an auxiliary charge pump output according to the detection signal; and   an auxiliary loop filter, arranged to receive the auxiliary charge pump output and generate the second control signal to the controllable oscillator according to the auxiliary charge pump output.   
     
     
         8 . The method of  claim 7 , wherein the auxiliary loop filter is a type I loop filter. 
     
     
         9 . The method of  claim 6 , wherein when the PLL operates in a normal operation mode, the phase alignment circuit is disabled. 
     
     
         10 . The method of  claim 6 , further comprising:
 a multiplexer, having a first input port, a second input port, and an output port, wherein the first input port is arranged to receive the detection signal, the second input port is arranged to receive the calibration signal, and the output port is arranged to output the detection signal to the charge pump circuit when the PLL operates in a normal operation mode, and output the calibration signal to the charge pump circuit when the PLL operates in the calibration mode.