Thin film transistor array panel and method of manufacturing the same

Abstract

A thin film transistor array panel that includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate; a gate insulating layer disposed between the gate electrode and the semiconductor layer; a source electrode disposed on the semiconductor layer and a drain electrode facing the source electrode; a metal oxide layer covering the source electrode and the drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the metal oxide layer, wherein the source electrode and the drain electrode include a first material and a second material which is added to the first material and metal included in the metal oxide layer is formed by diffusing the second material.

What is claimed is: 
     
         1 . A method for manufacturing a thin film transistor array panel,
 disposing a gate electrode on a substrate;   disposing a semiconductor layer on the substrate;   disposing a gate insulating layer between the gate electrode and the semiconductor layer;   disposing a source electrode on the semiconductor layer and a drain electrode facing the source electrode;   forming a metal oxide layer covering the source electrode and the drain electrode;   disposing a diffusion metal layer between the source electrode and the metal oxide layer and between the drain electrode and the metal oxide layer; and   forming a passivation layer covering the source electrode, the drain electrode, and the metal oxide layer,   wherein the source electrode and the drain electrode include a first material and a second material which is added to the first material and   wherein metal included in the metal oxide layer is the same as the second material.   
     
     
         2 . The method of  claim 1 , further comprised of forming the metal oxide layer to contact lateral walls of the diffusion metal layer. 
     
     
         3 . The method of  claim 2 , further comprised of including copper or a copper alloy in the formation of the source electrode and the drain electrode. 
     
     
         4 . The method of  claim 3 , further comprised of including at least one of Mn, Mg, Al, Mo, W, Ti, Ga, In, Ni, La, Nd, Sn, Ag, Cr, Zr, Zn, and Fe in the second material. 
     
     
         5 . The method of  claim 4 , further comprised of disposing barrier layers under the source electrode and the drain electrode, the barrier layer including metal oxide. 
     
     
         6 . The method of  claim 5 , further comprised of including one of indium-zinc oxide (IZO), gallium-zinc oxide (GZO), and aluminum-zinc oxide (AZO) in the barrier layer. 
     
     
         7 . The method of  claim 1 , further comprised of forming the metal oxide layer to cover upper surfaces and lateral walls of the source electrode and the drain electrode, respectively. 
     
     
         8 . The method of  claim 7 , further comprised of forming the passivation layer to contact the upper surface and the lateral wall of the metal oxide layer. 
     
     
         9 . The method of  claim 1 , further comprising:
 disposing barrier layers under the source electrode and the drain electrode; and   disposing capping layers over the source electrode and the drain electrode, the barrier layer and the capping layer including metal oxide.   
     
     
         10 . The method of  claim 9 , further comprised of:
 disposing lateral walls of the source electrode and the drain electrode, respectively, which are adjacent to a channel region of the semiconductor layer to be exposed and, covering the exposed lateral wall of the source electrode and the exposed lateral wall of the drain electrode with the metal oxide layer.   
     
     
         11 . The method of  claim 1 , further comprised of including an oxide semiconductor in the semiconductor layer. 
     
     
         12 . The method of  claim 1 , further comprised of aligning the lateral wall of the semiconductor layer like the lateral walls of the source electrode and the drain electrode, except for the channel region. 
     
     
         13 . A method for manufacturing a thin film transistor array panel, comprising:
 forming a gate electrode on a substrate;   forming a semiconductor layer on the substrate;   forming a gate insulating layer between the gate electrode and the semiconductor layer;   forming a source electrode disposed on the semiconductor layer and a drain electrode facing the source electrode;   annealing the source electrode and the drain electrode;   forming a metal oxide layer covering the source electrode and the drain electrode; and   forming a passivation layer covering the source electrode, the drain electrode, and the metal oxide layer,   wherein the annealing includes diffusing an alloyed material to surfaces of the source electrode and the drain electrode.   
     
     
         14 . The method of  claim 13 , subjecting the metal oxide layer to a treatment by nitrogen oxide when forming the metal oxide layer. 
     
     
         15 . The method of  claim 14 , wherein:
 in the annealing, the diffusion metal layer is formed between the source electrode and the metal oxide layer and between the drain electrode and the metal oxide layer, and the diffusion metal layer includes the alloyed material in the source electrode and the drain electrode.   
     
     
         16 . The method of  claim 15 , further comprised of prior to the forming of the source electrode and the drain electrode, forming a barrier layer on the semiconductor layer, wherein the barrier layer is formed to include the metal oxide. 
     
     
         17 . The method of  claim 16 , wherein:
 the metal oxide layer is formed to cover upper surfaces and lateral walls of the source electrode and the drain electrode, respectively.   
     
     
         18 . The method of  claim 17 , further comprising:
 prior to the formation of the source electrode and the drain electrode, forming a barrier layer on the semiconductor layer; and   forming capping layers on the source electrode and the drain electrode,   wherein the barrier layer and the capping layer are formed to include the metal oxide.   
     
     
         19 . The method of  claim 13 , wherein:
 the semiconductor layer is formed to include an oxide semiconductor.   
     
     
         20 . The method of  claim 13 , wherein:
 the forming of the semiconductor layer and the forming of the source electrode and the drain electrode are simultaneously performed using one mask.