Methods of forming a device including an interfacial dipole layer

Abstract

A method of forming an electronic device includes forming an oxygen scavenging layer proximate to a dielectric layer in a gate region of a field effect transistor (FET). The interface layer is between the dielectric layer and a substrate of the FET. The method further includes forming a dipole layer by annealing the oxygen scavenging layer, the dielectric layer, and the interface layer.

What is claimed is: 
     
         1 . A method of forming an integrated circuit that includes a memory device, the method comprising:
 forming an oxygen scavenging layer proximate to a dielectric layer in a gate region of a field effect transistor (FET), wherein an interface layer is between the dielectric layer and a substrate of the FET; and   forming a dipole layer by annealing the oxygen scavenging layer, the dielectric layer, and the interface layer.   
     
     
         2 . The method of  claim 1 , wherein the FET is a fin FET (FinFET). 
     
     
         3 . The method of  claim 1 , wherein the FET is a planar FET. 
     
     
         4 . The method of  claim 1 , wherein the substrate is a planar silicon substrate of a planar FET or a fin of a fin FET (FinFET). 
     
     
         5 . The method of  claim 1 , further comprising removing the oxygen scavenging layer after forming the dipole layer. 
     
     
         6 . The method of  claim 5 , further comprising:
 depositing a barrier layer on the dipole layer after removing the oxygen scavenging layer;   depositing a metal layer on the barrier layer;   depositing a second barrier layer on the metal layer; and   depositing a fill metal layer on the second barrier layer.   
     
     
         7 . The method of  claim 1 , wherein the FET is configured to store data, and wherein the integrated circuit further includes one or more logic devices. 
     
     
         8 . The method of  claim 7 , further comprising forming a protective layer over a region corresponding to the one or more logic devices before forming the oxygen scavenging layer. 
     
     
         9 . The method of  claim 8 , further comprising:
 removing the protective layer after forming the dipole layer to expose a cap layer of a logic device of the one or more logic devices;   depositing a barrier layer on the cap layer of the logic device and on the dipole layer of the memory device;   depositing a metal layer on the barrier layer;   depositing a second barrier layer on the metal layer; and   depositing a fill metal layer on the second barrier layer.   
     
     
         10 . The method of  claim 1 , wherein the FET is configured to store data based on an orientation of an electric dipole moment of the dipole layer. 
     
     
         11 . The method of  claim 1 , wherein the oxygen scavenging layer includes titanium nitride, the dielectric layer includes hafnium oxide (HfO 2 ), and the dipole layer includes hafnium silicon oxide (HfSiO 4 ). 
     
     
         12 . The method of  claim 1 , wherein the oxygen scavenging layer, the dielectric layer, and the interface layer are annealed at a temperature below about four hundred degrees Celsius. 
     
     
         13 . A non-transitory computer-readable medium comprising processor-executable instructions that, when executed by a processor, cause the processor to:
 initiate fabrication of an integrated circuit device, the integrated circuit device fabricated by:
 forming an oxygen scavenging layer proximate to a dielectric layer in a gate region of a field effect transistor (FET), wherein an interface layer is between the dielectric layer and a substrate of the FET; and 
 forming a dipole layer by annealing the oxygen scavenging layer, the dielectric layer, and the interface layer. 
   
     
     
         14 . The non-transitory computer-readable medium of  claim 13 , wherein the integrated circuit device is further fabricated by:
 removing the oxygen scavenging layer after forming the dipole layer;   depositing a barrier layer on the dipole layer after removing the oxygen scavenging layer;   depositing a metal layer on the barrier layer;   depositing a second barrier layer on the metal layer; and   depositing a fill metal layer on the second barrier layer.   
     
     
         15 . A method of forming an integrated circuit that includes a memory device, the method comprising:
 forming an oxygen scavenging layer proximate to a dielectric layer in a gate region of a field effect transistor (FET), wherein an interface layer is between the dielectric layer and a substrate of the FET; and   transforming the dielectric layer and the interface layer into a dipole layer to form a dipole at an interface of the dipole layer and the substrate by annealing the oxygen scavenging layer, the dielectric layer, and the interface layer.   
     
     
         16 . The method of  claim 15 , further comprising:
 forming a dummy oxide layer on the substrate between spacers of the FET;   forming a dummy fill layer proximate to the dummy oxide layer;   removing the dummy oxide layer and the dummy fill layer prior to forming the interface layer proximate to the substrate of the FET; and   removing the oxygen scavenging layer after forming the dipole layer.   
     
     
         17 . The method of  claim 16 , further comprising:
 depositing a barrier layer on the dipole layer after removing the oxygen scavenging layer;   depositing a metal layer on the barrier layer;   depositing a second barrier layer on the metal layer; and   depositing a fill metal layer on the second barrier layer.   
     
     
         18 . The method of  claim 15 , wherein the FET is configured to store data, and wherein the integrated circuit further includes one or more logic devices. 
     
     
         19 . The method of  claim 18 , further comprising:
 forming a protective layer over a region corresponding to the one or more logic devices before forming the oxygen scavenging layer;   removing the protective layer after forming the dipole layer to expose a cap layer of a logic device of the one or more logic devices;   depositing a barrier layer on the cap layer of the logic device and on the dipole layer of the memory device;   depositing a metal layer on the barrier layer;   depositing a second barrier layer on the metal layer; and   depositing a fill metal layer on the second barrier layer.   
     
     
         20 . The method of  claim 15 , wherein the interface layer includes silicon dioxide (SiO 2 ) and the dielectric layer includes hafnium oxide (HfO 2 ), and wherein annealing the oxygen scavenging layer, the dielectric layer, and the interface layer transforms the dielectric layer and the interface layer into a hafnium silicon oxide (HfSiO 4 ) layer.