Vertical memory devices and methods of manufacturing the same

Abstract

Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a first direction and extend in a second direction. The device may also include a first step pattern structure including extended gate lines extending from the gate lines and including first step layers and a second step pattern structure contacting the first step pattern structure, including the extended gate lines and including second step layers. An n-th extended gate line (n is an even number) may be disposed at an upper portion of each of the first step layers, and an (n−1)-th extended gate line may be disposed at an upper portion of each of the second step layers. Each of exposed portions of the (n−1)-th extended gate lines serves as a pad region, and the pad regions have different areas.

1 . A vertical memory device, comprising:
 a gate line structure including a plurality of gate lines spaced apart from each other in a first direction that is substantially perpendicular to a top surface of a substrate, each of the plurality of gate lines extending in a second direction substantially parallel to the top surface of the substrate;   a vertical channel structure extending through the plurality of gate lines in the first direction;   a plurality of extended gate lines, each of the plurality of extended gate lines extending from an edge portion of one of the plurality of gate lines in the second direction;   a first step pattern structure including a plurality of first step layers, each of the plurality of first step layers including an (n−1)-th one of the plurality of extended gate lines from the substrate and an n-th one of the plurality of extended gate lines from the substrate, and n being an even number that is equal to or greater than 2; and   a second step pattern structure contacting a sidewall of the first step pattern structure and including a plurality of second step layers, each of the plurality of second step layers including the (n−1)-th one of the plurality of extended gate lines from the substrate and the n-th one of the plurality of extended gate lines from the substrate, each of the n-th ones of the plurality of extended gate lines including a recessed portion at an end portion thereof in the second direction, and each of the (n−1)-th ones of the plurality of extended gate lines including an exposed portion that is exposed by the recessed portion of one of the n-th ones of the plurality of extended gate lines that is directly above a respective one of the (n−1)-th ones of the plurality of extended gate lines,   wherein areas of the exposed portions of the (n−1)-th ones of the plurality of extended gate lines are different.   
     
     
         2 . The vertical memory device of  claim 1 , wherein widths of the exposed portions of the (n−1)-th ones of the plurality of extended gate lines in a third direction that is substantially perpendicular to the second direction decrease as a height, in the first direction, of the each of the (n−1)-th ones of the plurality of extended gate lines increases. 
     
     
         3 . The vertical memory device of  claim 1 , wherein the gate line structure has a first width in a third direction that is substantially perpendicular to the second direction, and a sum of widths of the first and second step pattern structures in the third direction is substantially equal to the first width. 
     
     
         4 . The vertical memory device of  claim 3 , wherein the areas of the exposed portions of the (n−1)-th ones of the plurality of the extended gate lines decrease as a height, in the first direction, of the each of the (n−1)-th ones of the plurality of extended gate lines increases. 
     
     
         5 . The vertical memory device of  claim 1 , wherein each of the exposed portions of the (n−1)-th ones of the plurality of the extended gate lines has a rounded corner that is adjacent an interface between the first and second step pattern structures and is spaced apart from an edge of the each of the exposed portions of the (n−1)-th ones of the plurality of the extended gate lines in the second direction. 
     
     
         6 . The vertical memory device of  claim 5 , wherein a sidewall of each of the plurality of first step layers adjacent one of the rounded corners of the exposed portions of the (n−1)-th ones of the plurality of the extended gate lines has a curved shape. 
     
     
         7 . The vertical memory device of  claim 1 , further comprising a plurality of insulation layers, wherein each of the plurality of insulation layers is between first and second ones of the gate lines that are adjacent in the first direction and is between first and second ones of the extended gate lines that are adjacent in the first direction. 
     
     
         8 . The vertical memory device of  claim 1 , wherein the gate line structure and the first and second step pattern structures comprise a gate structure, and the vertical memory device includes a plurality of gate structures spaced apart from each other in a third direction that is substantially perpendicular to the second direction. 
     
     
         9 . The vertical memory device of  claim 8 , further comprising an opening between first and second ones of the gate structures that are adjacent in the third direction, wherein the opening extends in the second direction. 
     
     
         10 . The vertical memory device of  claim 9 , wherein the first and second ones of the gate structures are symmetric with respect to the opening. 
     
     
         11 . The vertical memory device of  claim 8 , wherein widths of the exposed portions of the (n−1)-th ones of the plurality of extended gate lines in the third direction decrease as a height, in the first direction, of the each of the (n−1)-th ones of the plurality of extended gate lines increases. 
     
     
         12 .- 24 . (canceled) 
     
     
         25 . A vertical memory device, comprising:
 a gate line structure including a plurality of gate lines spaced apart from each other in a first direction that is substantially perpendicular to a top surface of a substrate, each of the plurality of gate lines extending in a second direction that is substantially parallel to the top surface of the substrate;   vertical channel structures, each of the vertical channel structures extending through the plurality of gate lines in the first direction;   a first step pattern structure including a plurality of extended gate lines, each of the plurality of extended gate lines extending from an edge portion of one of the plurality of gate lines in the second direction, the first step pattern structure including a plurality of first step layers, each of the plurality of first step layers including a first pad region at an end portion thereof in the second direction, each of the first pad regions including an n-th one of the plurality of extended gate lines from the substrate as an uppermost one, relative to the substrate, of ones of the plurality of extended gate lines that are included in one of the plurality of first step layers, and n being an even number that is equal to or greater than 2; and   a second step pattern structure contacting a sidewall of the first step pattern structure and including the plurality of extended gate lines, the second step pattern structure including a plurality of second step layers, each of the plurality of second step layers including a second pad region at an end portion thereof in the second direction, and each of the second pad regions including an (n−1)-th one of the plurality of extended gate lines from the substrate as an uppermost one, relative to the substrate, of ones of the plurality of extended gate lines that are included in one of the plurality of second step layers,   wherein each of the second pad regions has a rounded corner that is adjacent an interface between the first and second step pattern structures and is spaced apart from an edge of the each of the second pad regions in the second direction.   
     
     
         26 . The vertical memory device of  claim 25 , wherein a sidewall of the first step pattern structure adjacent one of the rounded corners of the second pad regions has a curved shape. 
     
     
         27 . The vertical memory device of  claim 25 , wherein respective areas of the second pad regions are different. 
     
     
         28 .- 35 . (canceled) 
     
     
         36 . A vertical memory device, comprising:
 a plurality of gate lines on a substrate, the plurality of gate lines being stacked along a first direction that is substantially perpendicular to a top surface of the substrate, and each of the plurality of gate lines extending longitudinally in a second direction that is substantially parallel to the top surface of the substrate; and   a plurality of step layers, each of the plurality of step layers comprising a first extended gate line and a second extended gate line sequentially stacked on the substrate,   wherein each of the first and second extended gate lines extends from an edge portion of one of the plurality of gate lines in the second direction,   wherein each of the second extended gate lines comprises a recessed portion that extends for only a portion of the each of the second extended gate lines in a third direction that is substantially perpendicular to the second direction and exposes a pad region of each of the first extended gate lines that is directly below the each of the second extended gate lines, and   wherein a first one of the first extended gate lines is between the substrate and a second one of the first extended gate lines, a first pad region of the first one of the first extended gate lines comprises an end portion that has a first width in the third direction, and a second pad region of the second one of the first extended gate lines comprises an end portion that has a second width in the third direction that is less than the first width of the end portion of the first pad region.   
     
     
         37 . The vertical memory device of  claim 36 , wherein the first pad region of the first one of the first extended gate lines has a first area and the second pad region of the second one of the first extended gate lines has a second area that is less than the first area. 
     
     
         38 . The vertical memory device of  claim 36 , wherein a third one of the first extended gate lines is between the first one of the first extended gate lines and the second one of the first extended gate lines, and a third pad region of the third one of the first extended gate lines comprises an end portion that has a third width in the third direction that is less than the first width of the end portion of the first pad region and is greater than the second width of the end portion of the second pad region. 
     
     
         39 . The vertical memory device of  claim 36 , wherein each of the recessed portions of the second extended gate lines has a rounded corner between sidewalls of the each of the recessed portions of the second extended gate lines. 
     
     
         40 . The vertical memory device of  claim 36 , wherein the first pad region has a width in the third direction tapered toward the plurality of gate lines. 
     
     
         41 . The vertical memory device of  claim 36 , wherein the plurality of gate lines comprises a plurality of first gate lines, the plurality of step layers comprises a plurality of first step layers, each of the plurality of first step layers comprises the first extended gate line and the second extended gate line, and the recessed portions of the second extended gate lines comprise first recessed portions, and
 wherein the vertical memory device further comprises:   a plurality of second gate lines, each of the plurality of second gate lines extending longitudinally in the second direction; and   a plurality of second step layers, each of the plurality of second step layers comprises a third extended gate line and a fourth extended gate line sequentially stacked on the substrate,   wherein each of the third and fourth extended gate lines extends from an edge portion of one of the plurality of second gate lines in the second direction,   wherein each of the fourth extended gate lines comprises a second recessed portion that extends for only a portion of the each of the fourth extended gate lines in the third direction and exposes a pad region of each of the third extended gate lines that is directly below the each of the fourth extended gate lines, and   wherein one of the second extended gate lines and one of the fourth extended gate lines are coplanar, and the first recessed portion of the one of the second extended gate lines is a mirror image of the second recessed portion of the one of the fourth extended gate lines about an axis extending between the plurality of first step layers and the plurality of second step layers.