Discrete Power Transistor Package Having Solderless DBC To Leadframe Attach

Abstract

A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.

1 - 18 . (canceled) 
     
     
         19 . A method comprising:
 attaching a first metal layer of a direct-bonded copper (“DBC”) substrate to at least one lead with an ultrasonic weld thereby forming an assembly, wherein the ultrasonic weld mechanically and electrically couples the first metal layer to the lead, wherein the DBC substrate comprises an insulative layer disposed between the first metal layer and a second metal layer, and wherein an entire surface of the first metal layer contacts the insulative layer after the attaching;   attaching one and only one power semiconductor integrated circuit die to the first metal layer of the assembly;   surrounding at least the first metal layer and the one and only one power semiconductor integrated circuit die with an amount of encapsulant;   leaving at least a portion of the second metal layer of the DBC substrate exposed to form a back side of a packaged power integrated circuit device; and   leaving a portion of the lead exposed, wherein the second metal layer is electrically insulated from the first metal layer, and wherein the packaged power integrated circuit device comprises only one semiconductor die.   
     
     
         20 . The method of  claim 19 , wherein the packaged power integrated circuit device conforms to a TO-247 package outline. 
     
     
         21 . The method of  claim 19 , wherein the ultrasonic weld is formed by clamping the DBC substrate and the at least one lead together with not more than about 0.05 Mpa. 
     
     
         22 . The method of  claim 19 , wherein the ultrasonic weld is formed using ultrasonic vibrations of an amplitude of less than approximately 20 micrometers. 
     
     
         23 . The method of  claim 19 , wherein the ultrasonic weld decreases a thickness of a region of the first metal layer in contact with the at least one lead by about 0.05 millimeters. 
     
     
         24 . The method of  claim 19 , wherein the first metal layer has a thickness of at least 0.25 millimeters. 
     
     
         25 . A packaged power integrated circuit device comprising:
 a direct-bonded copper (“DBC”) substrate comprising an insulative layer disposed between a first metal layer and a second metal layer;   one and only one power semiconductor integrated circuit die attached to the first metal layer;   at least one lead of a leadframe having a substantially planar surface that is mechanically and electrically coupled to the first metal layer with an ultrasonic weld that decreases a thickness of a region of the first metal layer in contact with the planar surface without separation between the insulative layer and the metal layers of the DBC substrate; and   an amount of encapsulant surrounding the one and only one power semiconductor integrated circuit die and at least the first metal layer, and leaving at least a portion of the second metal layer of the DBC substrate exposed to form a back side of the packaged power integrated circuit device, and leaving a portion of the lead exposed, wherein the second metal layer is electrically insulated from the first metal layer.   
     
     
         26 . The packaged power integrated circuit device of  claim 25 , wherein an upper surface of the at least one lead includes nonplaner indentations formed by the ultrasonic weld. 
     
     
         27 . The packaged power integrated circuit device of  claim 25 , wherein the ultrasonic weld is carried out by clamping the DBC substrate and the at least one lead together with not more than about 0.05 Mpa 
     
     
         28 . The packaged power integrated circuit device of  claim 25 , wherein the welding is carried out using ultrasonic vibrations of an amplitude of less than approximately 20 micrometers. 
     
     
         29 . The packaged power integrated circuit device of  claim 25 , wherein the first metal layer has a thickness of at least 0.25 millimeters. 
     
     
         30 . The packaged power integrated circuit device of  claim 25 , wherein the ultrasonic weld decreases the thickness of the region of the first metal layer in contact with the planar surface by about 0.05 millimeters. 
     
     
         31 . The packaged power integrated circuit device of  claim 25 , wherein the packaged power integrated circuit device conforms to a TO-247 package outline. 
     
     
         32 . The packaged power integrated circuit device of  claim 25 , wherein the one and only one power semiconductor integrated circuit die is taken from the group consisting of: a power rectifier die, a power regulator die, a silicon controlled rectifier die, a power bipolar transistor integrated circuit die, a power insulated gate bipolar transistor circuit die, and a power field effect transistor integrated circuit die. 
     
     
         33 . The packaged power integrated circuit device of  claim 25 , wherein the packaged power integrated circuit device includes three leads, and wherein the back side of the packaged power integrated circuit device is electrically insulated from each of the three leads. 
     
     
         34 . The packaged power integrated circuit device of  claim 25 , wherein there is no solder disposed between the first metal layer of the DBC substrate and the one and only one power semiconductor integrated circuit die. 
     
     
         35 . A packaged power integrated circuit device comprising:
 a direct-bonded copper (“DBC”) substrate comprising an insulative layer disposed between the first metal layer and a second metal layer;   one and only one power semiconductor integrated circuit die attached to the first metal layer;   at least one lead that is coupled to the first metal layer with an ultrasonic weld formed using ultrasonic vibrations having an amplitude of less than or equal to 20 micrometers and by clamping the DBC substrate and the at least on lead together with no more than 0.05 Mpa, wherein a surface of the first metal layer entirely contacts the insulative layer of the DBC substrate after the ultrasonic weld is formed; and   an amount of encapsulant surrounding the one and only one power semiconductor integrated circuit die and at least the first metal layer, leaving at least a portion of the second metal layer of the DBC substrate exposed to form a back side of the packaged power integrated circuit device, and leaving a portion of the lead exposed, wherein the second metal layer is electrically insulated from the first metal layer.   
     
     
         36 . The packaged power integrated circuit device of  claim 35 , wherein the first metal layer has a thickness of at least 0.25 millimeters. 
     
     
         37 . The packaged power integrated circuit device of  claim 35 , wherein the ultrasonic weld decreases the thickness of the region of the first metal layer in contact with the planar surface by about 0.05 millimeters. 
     
     
         38 . The packaged power integrated circuit device of  claim 35 , wherein the packaged power integrated circuit device conforms to a TO-247 package outline.