Memory refresh method and devices

Abstract

The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.

1 . A memory controller that controls a memory device including a stack of dynamic random access memory (DRAM) dies, each DRAM die including a plurality of banks, each bank of the plurality of banks having a respective plurality of memory cells, the memory controller comprising:
 a first circuit to generate a refresh command that specifies a bank address of a first bank of the plurality of banks and a first row address of memory cells within the bank that have not been opportunistically refreshed by the memory device;   and   a second circuit configured to output the refresh command to the memory device.   
     
     
         2 . The memory controller of  claim 1 , wherein the second circuit is further configured to:
 receive a request from the memory device to issue one or more refresh commands to the memory device responsive to a time interval elapsing since the memory device last performed a refresh on the memory cells within the plurality of banks; and   provide an acknowledgement to the memory device indicating approval of the request for the memory controller to issue one or more refresh commands;   wherein the first circuit generates the refresh command responsive to the second circuit receiving the request.   
     
     
         3 . The memory controller of  claim 2 , wherein the first circuit further generates a plurality of refresh commands to refresh rows within a plurality of banks within the memory device responsive to receiving the request. 
     
     
         4 . The memory controller of  claim 2 , wherein the second circuit is configured to provide the acknowledgement after a delay period that allows the memory device to complete all pending opportunistic refreshes of the memory device. 
     
     
         5 . The memory controller of  claim 1 , wherein an opportunistic refresh of the memory device is a refresh of memory cells within at least one bank of the plurality of banks concurrently with an activation of memory cells in another one of the plurality of banks. 
     
     
         6 . The memory controller of  claim 1 , wherein the first circuit is further configured to generate an activate command and a data access command, the activate command specifying a second bank address and a second row address, the second bank address identifying a second bank of the plurality of banks in the memory device for a memory access, and the second row address identifying a second row of memory cells within the second bank of the memory device for the memory access; and
 wherein the second circuit is further configured to output the activate command and the data access command generated by the first circuit to the memory device, the second circuit configured to receive data that is sensed from the second row of memory cells within the second bank based the data access command, the data from the second row of memory cells within the first bank sensed while a third row of memory cells within a third bank is refreshed opportunistically.   
     
     
         7 . The memory controller of  claim 1 , wherein the first circuit is configured to generate the activate command and the data access command responsive to receiving a data access request from a computer resource; and
 wherein the second circuit is further configured to store sequences of activate commands and refresh commands received from the first circuit.   
     
     
         8 . The memory controller of  claim 7 , further comprising:
 an interface configured to output the sequences of activate commands and refresh commands stored in the second circuit to the memory device.   
     
     
         9 . A method of operation of a memory controller that controls a memory device that includes a stack of dynamic random access memory (DRAM) dies, each DRAM die including a plurality of banks, each bank of the plurality of banks having a respective plurality of memory cells, the method comprising:
 generating a refresh command that specifies a bank address of a first bank of the plurality of banks and a first row address of memory cells within the bank that have not been opportunistically refreshed by the memory device; and   outputting the refresh command to the memory device.   
     
     
         10 . The method of  claim 9 , further comprising:
 receiving a request from the memory device to issue one or more refresh commands to the memory device responsive to a time interval elapsing since the memory device last performed a refresh on the memory cells within the plurality of banks; and   providing an acknowledgement to the memory device indicating approval of the request for the memory controller to issue one or more refresh commands;   wherein the refresh command is generated responsive to receiving the request.   
     
     
         11 . The method of  claim 10 , further comprising:
 generating a plurality of refresh commands to refresh rows within a plurality of banks within the memory device responsive to receiving the request.   
     
     
         12 . The memory controller of  claim 10 , wherein the acknowledgement is wherein the provided after a delay period that allows the memory device to complete all pending opportunistic refreshes of the memory device. 
     
     
         13 . The method of  claim 9 , wherein an opportunistic refresh of the memory device is a refresh of memory cells within at least one bank of the plurality of banks concurrently with an activation of memory cells in another one of the plurality of banks. 
     
     
         14 . The method of  claim 9 , further comprising:
 generating an activate command and a data access command, the activate command specifying a second bank address and a second row address, the second bank address identifying a second bank of the plurality of banks in the memory device for a memory access, and the second row address identifying a second row of memory cells within the second bank of the memory device for the memory access;   outputting the activate command and the data access command to the memory device; and   receiving data that is sensed from the second row of memory cells within the second bank based the data access command, the data from the second row of memory cells within the first bank sensed while a third row of memory cells within a third bank is refreshed opportunistically.   
     
     
         15 . A memory controller that controls a memory device including a stack of dynamic random access memory (DRAM) dies, each DRAM die including a plurality of banks, each of the plurality of banks having a plurality of memory cells, the memory controller comprising:
 a transaction generator circuit configured to generate a refresh command that specifies a bank address of a first bank of the plurality of banks and a first row address of memory cells within the bank that have not been opportunistically refreshed by the memory device;   a transaction queue circuit configured to store the refresh command generated by the transaction generator circuit; and   an interface circuit configured to output the refresh command to the memory device.   
     
     
         16 . The memory controller of  claim 15 , wherein the transaction queue is further configured to:
 receive a request from the memory device to issue one or more refresh commands to the memory device responsive to a time interval elapsing since the memory device last performed a refresh on the memory cells within the plurality of banks;   wherein the interface circuit is configured to output an acknowledgement to the memory device indicating approval of the request for the memory controller to issue one or more refresh commands; and   wherein the transaction generator circuit is further configured to generate the refresh command responsive to the transaction queue receiving the request.   
     
     
         17 . The memory controller of  claim 16 , wherein the transaction generator circuit is further configured to generate a plurality of refresh commands to refresh rows within a plurality of banks within the memory device responsive to receiving the request. 
     
     
         18 . The memory controller of  claim 16 , wherein the interface circuit outputs the acknowledgement after a delay period that allows the memory device to complete all pending opportunistic refreshes of the memory device. 
     
     
         19 . The memory controller of  claim 15 , wherein an opportunistic refresh of the memory device is a refresh of memory cells within at least one bank of the plurality of banks concurrently with a data access of memory cells in another one of the plurality of banks. 
     
     
         20 . The memory controller of  claim 15 , wherein the transaction generator circuit is further configured to generate an activate command and a data access command, the activate command specifying a second bank address and a second row address, the second bank address identifying a second bank of the plurality of banks in the memory device for a memory access, and the second row address identifying a second row of memory cells within the second bank of the memory device for the memory access; wherein the transaction queue is further configured to store the activate command and the data access command generated by the transaction generator circuit; and
 wherein the interface circuit is configured to output the stored activate command and the data access command to the memory device;   wherein the transaction queue is further configured to receive data that is sensed from the second row of memory cells within the second bank based the data access command, the data from the second row of memory cells within the first bank sensed while a third row of memory cells within a third bank is refreshed opportunistically.