Scan frame based test access mechanisms

Abstract

Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.

What is claimed is: 
     
         1 . A test access mechanism comprising:
 (a) a mechanism serial input and a mechanism serial output;   (b) a core having parallel scan paths, each scan path having a stimulus input and a response output;   (c) a scan input register having an input coupled to the mechanism serial input and including stimulus registers with parallel stimulus outputs coupled to the stimulus inputs, mask registers coupled in series with the stimulus registers and having parallel mask outputs, and a control register coupled in series with the stimulus registers and the mask registers and having a control output; and   (d) compressor circuitry having parallel inputs coupled to the response outputs, parallel mask inputs coupled to the parallel mask outputs, and a compressed output coupled to the mechanism serial output.   
     
     
         2 . The test access mechanism of  claim 1  including an update register coupled between the parallel mask outputs and the parallel mask inputs. 
     
     
         3 . The test access mechanism of  claim 1  including an update register coupled between the parallel mask outputs and the parallel mask inputs and an enable input coupled to the update register. 
     
     
         4 . The test access mechanism of  claim 1  in which the scan input register is a scan frame input register including a series connection with the mechanism serial input of the serial stimulus registers, the serial mask registers, and the control register. 
     
     
         5 . The test access mechanism of  claim 1  in which the scan input register is a scan frame input register including a series connection with the mechanism serial input of the serial stimulus registers, the serial mask registers, the control register, and a frame marker register. 
     
     
         6 . A test access mechanism comprising:
 (a) a mechanism serial input and a mechanism serial output;   (b) a core having parallel scan paths, each scan path having a stimulus input and a response output;   (c) a scan input register having, including serial stimulus registers with an input coupled to the mechanism serial input and parallel stimulus outputs coupled to the stimulus inputs and serial mask registers coupled in series with the stimulus registers and having parallel mask outputs; and   (d) compressor circuitry having parallel inputs coupled to the response outputs, parallel mask inputs coupled to the parallel mask outputs, and a compressed output coupled to the mechanism serial output.   
     
     
         7 . The test access mechanism of  claim 6  including an update register coupled between the parallel mask outputs and the parallel mask inputs. 
     
     
         8 . The test access mechanism of  claim 6  including an update register coupled between the parallel mask outputs and the parallel mask inputs and an enable input coupled to the update register. 
     
     
         9 . The test access mechanism of  claim 6  including a control register coupled in series with the mechanism serial input and having a control output. 
     
     
         10 . The test access mechanism of  claim 6  including a control register coupled in series with the serial stimulus registers and serial mask registers and having a control output, and including an update register having a control input coupled to the control output and having an update control output. 
     
     
         11 . The test access mechanism of  claim 6  in which the scan input register is a scan frame input register including a series connection with the mechanism serial input of the serial stimulus registers, the serial mask registers, and a control register. 
     
     
         12 . The test access mechanism of  claim 6  in which the scan input register is a scan frame input register including a series connection with the mechanism serial input of the serial stimulus registers, the serial mask registers, a control register, and a frame marker register.