Semiconductor device and method of manufacturing same

Abstract

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes: providing a workpiece having a recess and a dielectric layer lining the recess; forming a conductive structure within the recess, wherein the conductive structure partially fills the recess; and recessing the dielectric layer, wherein, after the recessing, a top surface of the recessed dielectric layer is disposed within the recess.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a workpiece having a recess;   a dielectric layer lining a portion of the recess; and   a conductive structure within the recess, wherein:
 the conductive structure is disposed within the recess; 
 an uppermost surface of the dielectric layer is disposed below an uppermost portion of the recess; and 
 an uppermost surface of the conductive structure is at a substantially same level as the uppermost surface of the dielectric layer. 
   
     
     
         2 . The semiconductor device of  claim 1 , further comprising an insulating layer disposed over the uppermost surface of the dielectric layer and the uppermost surface of the conductive structure. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the conductive structure comprises a gate electrode. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the dielectric layer comprises a dielectric material having a dielectric constant greater than or substantially equal to about 5. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the workpiece comprises an insulating material. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the conductive structure is a gate of a FinFET structure. 
     
     
         7 . The semiconductor device of  claim 1 , wherein sidewalls of the recess are tapered. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the conductive structure comprises a conductive liner and a conductive layer. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the dielectric layer comprises a thickness of about 40 angstroms. 
     
     
         10 . A semiconductor device, comprising:
 a substrate;   a fin structure on the substrate;   a first insulating layer over the fin structure;   an opening in the first insulating layer, the opening disposed over a top surface of the fin structure, wherein the opening extends from the top surface of the fin structure to a top surface of the first insulating layer;   a dielectric layer lining a portion of the opening, wherein a topmost surface of the dielectric layer is lower than the top surface of the first insulating layer; and   a conductive structure over the dielectric layer, wherein a topmost surface of the conductive structure is below the top surface of the first insulating layer.   
     
     
         11 . The semiconductor device of  claim 10 , wherein the topmost surface of the dielectric layer is disposed at a substantially same level as the topmost surface of the conductive structure. 
     
     
         12 . The semiconductor device of  claim 11 , further comprising a second insulating layer over the conductive structure and over the dielectric layer, wherein the second insulating layer covers a top surface of the dielectric layer and the top surface of the conductive structure. 
     
     
         13 . The semiconductor device of  claim 12 , wherein the conductive structure comprises a conductive liner over the dielectric layer and a conductive layer over the conductive liner. 
     
     
         14 . The semiconductor device of  claim 13 , further comprising an etch stop layer interposed between the fin structure and the first insulating layer. 
     
     
         15 . The semiconductor device of  claim 14 , wherein the fin structure comprises a source region and a drain region, wherein the opening is disposed between the source region and the drain region. 
     
     
         16 . A semiconductor device, comprising:
 a substrate;   a first insulating layer over the substrate, the first insulating layer having a recess;   a dielectric layer disposed in the recess, the dielectric layer lining sidewalls of the recess, the dielectric layer lining a top surface of the substrate;   a conductive structure disposed on the dielectric layer, wherein top surfaces of the dielectric layer are disposed at a substantially same level as a top surface of the conductive structure;   a second insulating layer over the dielectric layer and the conductive structure, wherein the second insulating layer comprises a bottommost surface below the top surface of the first insulating layer, the second insulating layer in contact with sidewalls of the recess;   and an isolation structure disposed within the substrate.   
     
     
         17 . The semiconductor device of  claim 16 , wherein the recess has a depth of about 75 nanometers. 
     
     
         18 . The semiconductor device of  claim 16 , further comprising a source region and a drain region, wherein the recess is over and interposed between the source region and the drain region. 
     
     
         19 . The semiconductor device of  claim 18 , wherein the conductive structure is a gate electrode. 
     
     
         20 . The semiconductor device of  claim 19 , wherein sidewalls of the recess are substantially straight and oriented in a direction normal to a major surface of the substrate.