Cointegration of directed self assembly and sidewall image transfer patterning for sublithographic patterning with improved design flexibility

Abstract

After forming transfer layer portions over a portion of a dielectric cap layer overlying a first portion of a substrate by a directed self-assembly process, a hard mask layer is formed over the dielectric cap layer to fill spaces between the transfer layer portions. Spacers are then formed over a portion of the hard mask layer overlying a second portion of the substrate by a sidewall image transfer process. A top semiconductor layer of the substrate is subsequently patterned using the transfer layer portions and the spacers as an etch mask to provide densely packed semiconductor fins in the first region and semi-isolated semiconductor fins in the second region of the substrate.

What is claimed is: 
     
         1 . A semiconductor structure comprising:
 a plurality of first semiconductor fins located in a first region of a substrate and having a first pitch; and   a plurality of second semiconductor fins located in a second region of the substrate and having a second pitch that is equal to a non-integer multiple of the first pitch.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the second pitch is 1.5 times the first pitch. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein each of the plurality of first semiconductor fins has a width less than 50 nm. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein each of the plurality of second semiconductor fins has a width ranging from 5 nm to 10 nm. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein the first region is a logic device region and the second region is a static random access memory (SRAM) device region. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein the first pitch is equal to a natural pitch of a directed self-assembly (DSA) material being used. 
     
     
         7 . The semiconductor structure of  claim 1 , wherein a spacing between adjacent first semiconductor fins in the plurality of first semiconductor fins is determined by a domain size of the DSA material being used. 
     
     
         8 . The semiconductor structure of  claim 7 , wherein the spacing between adjacent first semiconductor fins in the plurality of first semiconductor fins is less than 50 nm. 
     
     
         9 . The semiconductor structure of  claim 7 , wherein the DSA material comprises a diblock copolymer, a triblock copolymer, a blend of homopolymers, a blend of copolymers, and a combination thereof. 
     
     
         10 . The semiconductor structure of  claim 9 , wherein the DSA material comprises poly(styrene-block-methyl methacrylate) (PS-b-PMMA), poly(ethylene oxide-block-isoprene) (PEO-b-PI), poly(ethylene oxide-block-butadiene) (PEO-b-PBD), poly(ethylene oxide-block-styrene) (PEO-b-PS), poly(ethylene oxide-block-methylmethacrylate) (PEO-b-PMMA), poly(ethyleneoxide-block-ethylethylene) (PEO-b-PEE), poly(styrene-block-vinylpyridine) (PS-b-PVP), poly(styrene-block-isoprene) (PS-b-PI), poly(styrene-block-butadiene) (PS-b-PBD), poly(styrene-block-ferrocenyldimethylsilane) (PS-b-PFS), poly(butadiene-block-vinylpyridine) (PBD-b-PVP), poly(isoprene-block-methyl methacrylate) (PI-b-PMMA), poly(styrene-block-lactic acid) (PS-b-PLA) or poly(styrene-block-dymethylsiloxane) (PS-b-PDMS). 
     
     
         11 . The semiconductor structure of  claim 1 , wherein a spacing between adjacent second semiconductor fins in the plurality of second semiconductor fins is defined by a minimum pitch of an associated lithographic process. 
     
     
         12 . The semiconductor structure of  claim 1 , wherein each of the plurality of first semiconductor fins and the plurality of second semiconductor fins comprises Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs or InP. 
     
     
         13 . The semiconductor structure of  claim 1 , wherein the substrate comprises a handle substrate and an insulator layer overlying the handle substrate, wherein the plurality of first semiconductor fins and the plurality of second semiconductor fins are in contact with a top surface of the insulator layer. 
     
     
         14 . The semiconductor structure of  claim 11 , wherein the insulator layer comprises silicon oxide, silicon nitride, silicon oxynitride, boron nitride or a combination thereof. 
     
     
         15 . The semiconductor structure of  claim 1 , wherein each of the plurality of first semiconductor fins and the plurality of second semiconductor fins has a height ranging from 10 nm to 200 nm.