Pci express enhancements

Abstract

An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.

1 - 33 . (canceled) 
     
     
         34 . An apparatus comprising:
 I/O logic to:
 identify that a link is to exit an active state, wherein the link comprises a plurality of lanes; 
 maintain parity information for the lanes based on data previously sent over the link; and 
 send an indication of the parity information prior to the exit from the active state. 
   
     
     
         35 . The apparatus of  claim 34 , wherein the indication of the parity information is sent in response to the exit. 
     
     
         36 . The apparatus of  claim 34 , wherein the indication of the parity information is sent in an ordered set. 
     
     
         37 . The apparatus of  claim 36 , wherein the indication of the parity information for each lane is included in a respective parity bit for each lane included in the ordered set. 
     
     
         38 . The apparatus of  claim 36 , wherein the ordered set comprises a skip (SKP) ordered set (OS). 
     
     
         39 . The apparatus of  claim 34 , wherein the link is to exit the active state based on a link recovery. 
     
     
         40 . The apparatus of  claim 39 , wherein the link recovery is based on a detected error on the link. 
     
     
         41 . The apparatus of  claim 40 , wherein the error comprises a framing token error. 
     
     
         42 . At least one machine accessible storage medium having code stored thereon, the code when executed on a machine, causes the machine to:
 transmit data on a link comprising a plurality of lanes;   maintain parity information for each of the lanes based on the transmitted data;   identify that the link is to exit an active state; and   send the parity information prior to the exit from the active state.   
     
     
         43 . The storage medium of  claim 42 , wherein the parity information is sent in a skip (SKP) ordered set (OS). 
     
     
         44 . The storage medium of  claim 42 , wherein the parity information is to be sent prior to a scheduled sending of parity information based on identifying that the link is to exit the active state. 
     
     
         45 . The storage medium of  claim 42 , wherein the link is to exit the active state based on a link recovery triggered by an error detected on the link. 
     
     
         46 . The storage medium of  claim 45 , wherein the code, when executed, further causes the machine to receive data indicating the error from a receiver device. 
     
     
         47 . An apparatus comprising:
 I/O logic to:
 maintain first parity information for each of a plurality of lanes of a link based on data previously sent over the link; 
 receive second parity information in response to an event, wherein the event is to cause the link to exit an active state and the second parity information is caused to be sent prior to the exit from the active state; and 
 compare the first parity information with the second information to identify potential lane errors on one or more of the lanes. 
   
     
     
         48 . The apparatus of  claim 47 , wherein the second parity information is included in an ordered set. 
     
     
         49 . The apparatus of  claim 48 , wherein the second parity information is included in parity bits included in the ordered set. 
     
     
         50 . The apparatus of  claim 48 , wherein the ordered set comprises a SKP OS. 
     
     
         51 . The apparatus of  claim 47 , wherein the link is to exit the active state based on a recovery of the link triggered by an error detected on the link. 
     
     
         52 . The apparatus of  claim 51 , wherein the error comprises a framing token error. 
     
     
         53 . The apparatus of  claim 47 , wherein the I/O logic is further to report potential lane errors to a lane error register. 
     
     
         54 . The apparatus of  claim 53 , wherein the lane error register comprises an LES register. 
     
     
         55 . A system comprising:
 a data link comprising a plurality of lanes;   a first device;   a second device communicatively coupled to the first device using the data link, the second device comprising I/O logic to:
 transmit data to the first device on the link; 
 maintain parity information for each of the lanes based on the transmitted data; 
 identify that the link is to exit an active state; and 
 send an indication of the parity information prior to the exit from the active state 
   
     
     
         56 . The system of  claim 55 , wherein the parity information comprises first parity information and the first device comprises I/O logic to:
 maintain second parity information for each of the lanes based on the data;   receive the indication of the first parity information; and   compare the first parity information with the second information to identify potential lane errors on one or more of the lanes.   
     
     
         57 . The system of claim  24 , wherein the I/O logic of the first device is further to determine a potential error involving a particular one of the lanes based on a comparison of the first parity information with the second information. 
     
     
         58 . The system of  claim 55 , wherein the indication of the parity information is included in a SKP OS sent by the second device to the first device.