Differential interface for inter-device communication in a battery management and protection system

Abstract

A multi-cell battery stack includes a microcontroller and a string of battery management and protection IC devices connected to one another in a daisy chain configuration. Each battery management and protection IC device can include a communication interface circuit that includes pairs of differential input signal lines, receivers including respective current comparator circuits to receive differential signals on the differential input signal lines, and transmitters to provide outgoing differential signals on the differential input signal lines. A digital circuit block allows signals to pass between the receivers and transmitters.

1 .- 13 . (canceled) 
     
     
         14 . A battery management and protection integrated circuit comprising a communication interface circuit that comprises:
 a shift register to store incoming sampled signals; and   a Manchester detector including a control unit and a plurality of XOR gates, wherein a respective pair of sampled signals in the shift register are fed to one or more of the XOR gates, and wherein the control unit determines whether or not the sampled signals are valid based on outputs of one or more of the XOR gates and adjusts a window size for valid data based thereon.   
     
     
         15 . The battery management and protection integrated circuit of  claim 14  wherein the control unit receives activates or deactivates one or more of the XOR gates based on an input signal indicative of a number of samples per symbol. 
     
     
         16 . The battery management and protection integrated circuit of  claim 15  wherein an oversampling rate indicative of the samples per symbol is detected by a clock recovery module and fed from the clock recovery module to the control unit. 
     
     
         17 . The battery management and protection integrated circuit of  claim 15  wherein the window size corresponds to a number of samples used by the Manchester detector to detect a symbol. 
     
     
         18 . The battery management and protection integrated circuit of  claim 17  wherein if one of the XOR gates is deactivated or if the output of one of the XOR gates is zero, then the control unit reduces the window size by one sample at the start of shift register and by one sample at the end of shift register. 
     
     
         19 . The battery management and protection integrated circuit of  claim 14  wherein the Manchester detector generates a decoded data bit based on the sampled signals in the shift register, and wherein the decoded data bit and a valid window size are fed from the Manchester detector to a clock recovery module to calculate a phase shift of symbols for correction of a symbol sampling clock. 
     
     
         20 . A battery management and protection integrated circuit device comprising a communication interface circuit that comprises:
 a shift register to store incoming sampled signals;   a clock recovery module; and   a Manchester detector that generates a decoded data bit based on the sampled signals in the shift register and determines a window size for valid data,   wherein the decoded data bit and the window size are provided to the clock recovery module to calculate a phase shift of symbols for correction of a symbol sampling clock that is provided to the Manchester detector.   
     
     
         21 . The battery management and protection integrated circuit of  claim 20  wherein the clock recovery module is operable to calculate the phase shift of symbols by performing operations including:
 counting a number samples in the shift register with the same value as the decoded data bit; 
 determining whether the number of samples in the shift register with the same value as the decoded data bit is greater or less than half the window size; and 
 determining whether a sampling point is too late or too early based on determining whether the number of samples in the shift register with the same value as the decoded data bit is greater or less than half the window size. 
 
     
     
         22 . The battery management and protection integrated circuit of  claim 21  the clock recovery module is further operable to perform operations including:
 feeding a symbol sampling point error to a low pass filter with a configurable length; and 
 using an output of the low pass filter to increase or decrease the number of samples until a next symbol sampling. 
 
     
     
         23 . A multi-cell battery stack comprising:
 a string of battery management and protection IC devices connected to one another in a daisy chain configuration; and   a microcontroller connected to the string of battery management and protection IC devices,   wherein communication between the battery management and protection IC devices occurs over differential DC isolated interfaces, and wherein each battery management and protection IC device comprises a communication interface circuit that includes:
 a first pair of differential input signal lines; 
 a first receiver comprising a first current comparator circuit to receive incoming differential signals on the first pair of differential input signal lines; 
 a first transmitter to provide outgoing differential signals on the first pair of differential input signal lines; 
 a second pair of differential input signal lines; 
 a second receiver comprising a second current comparator circuit to receive incoming differential signals on the second pair of differential input signal lines; 
 a second transmitter to provide outgoing differential signals on the second pair of differential input signal lines; and 
 a digital circuit block that allows signals to pass from the first receiver to the second transmitter and that allows signals to pass from the second receiver to the first transmitter, wherein the digital circuit block comprises circuitry to perform digital signal decoding and includes:
 a shift register to store incoming sampled signals; 
 a clock recovery module; and 
 a Manchester detector including a control unit and a plurality of logic gates, wherein a respective pair of sampled signals in the shift register are fed to one or more of the logic gates, and wherein the control unit determines whether or not the sampled signals are valid based on outputs of one or more of the logic gates and adjusts a window size for valid data based thereon, 
 wherein the Manchester detector generates a decoded data bit based on the sampled signals in the shift register and determines a window size for valid data, and 
 wherein the decoded data bit and the window size are provided to the clock recovery module to calculate a phase shift of symbols for correction of a symbol sampling clock that is provided to the Manchester detector.