Metal gate structure and method of formation
Abstract
Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures.
Claims
exact text as granted — not AI-modified1 .- 9 . (canceled)
10 . A semiconductor structure, comprising:
a semiconductor substrate; a fin formed on the semiconductor substrate; and a gate stack formed over the fin, wherein the gate stack comprises:
a work function metal layer disposed on the fin;
a metal fill layer disposed on the work function metal layer; and
a capping layer disposed on a top and side portions of the gate stack, wherein the work function metal layer terminates at the capping layer on the semiconductor substrate.
11 . The semiconductor structure of claim 10 , wherein the metal fill layer comprises tungsten.
12 . The semiconductor structure of claim 10 , wherein the work function metal layer comprises titanium.
13 . The semiconductor structure of claim 10 , wherein the work function metal layer comprises aluminum.
14 . The semiconductor structure of claim 10 , wherein the capping layer comprises silicon nitride.
15 . The semiconductor structure of claim 10 , wherein the capping layer comprises silicon oxide.
16 . A semiconductor structure, comprising:
a semiconductor substrate; a fin formed on the semiconductor substrate; and a gate stack formed over the fin, wherein the gate stack comprises:
a work function metal layer disposed on the fin;
a metal fill layer disposed on the work function metal layer; and
a capping layer disposed on a top and side portions of the gate stack wherein the work function metal layer terminates at the capping layer on the semiconductor substrate, and wherein the capping layer disposed on the side portions of the gate stack is disposed at a distance from the fin ranging from about 5 nanometers to about 15 nanometers.
17 . The semiconductor structure of claim 16 , wherein the metal fill layer comprises tungsten.
18 . The semiconductor structure of claim 16 , wherein the work function metal layer comprises titanium.
19 . The semiconductor structure of claim 16 , wherein the work function metal layer comprises aluminum.
20 . The semiconductor structure of claim 16 , wherein the capping layer comprises silicon nitride.
21 . The semiconductor structure of claim 16 , wherein the capping layer comprises silicon oxide.
22 . A semiconductor structure, comprising:
a semiconductor substrate; a fin formed on the semiconductor substrate; and a gate stack formed over the fin, wherein the gate stack comprises:
a work function metal layer disposed on the fin;
a metal fill layer disposed on the work function metal layer; and
a capping layer disposed on a top and side portions of the gate stack;
wherein the work function metal layer terminates at the capping layer on the semiconductor substrate, and wherein the capping layer disposed on the side portions of the gate stack is disposed at a distance from the fin less than about 20 nanometers.
23 . The semiconductor structure of claim 22 , wherein the metal fill layer comprises tungsten.
24 . The semiconductor structure of claim 22 , wherein the work function metal layer comprises titanium.
25 . The semiconductor structure of claim 22 , wherein the work function metal layer comprises aluminum.
26 . The semiconductor structure of claim 22 , wherein the capping layer comprises silicon nitride.
27 . The semiconductor structure of claim 10 , wherein the capping layer is in physical contact with the semiconductor substrate.
28 . The semiconductor structure of claim 16 , wherein the capping layer is in physical contact with the semiconductor substrate.
29 . The semiconductor structure of claim 22 , wherein the capping layer is in physical contact with the semiconductor substrate.Join the waitlist — get patent alerts
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