Semiconductor device contacts

Abstract

Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulating layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor substrate having a channel region therein;   a gate dielectric on the channel region;   a gate electrode on the gate dielectric;   a doped silicon source region and a doped silicon drain region, each adjacent the channel region such that the channel region is between the silicon source region and the silicon drain region; and   a transition layer in contact with the silicon source region and the silicon drain region, wherein the transition layer includes no silicide region on the silicon source region and no silicide region on the silicon drain region.   
     
     
         2 . The device of  claim 1 , wherein the substrate is p-doped and the silicon source and drain regions comprise n-doped silicon and the transition layer is selected from a group consisting of titanium nitride (TiN), zirconium nitride (ZrN), hafnium nitride (HfN), tantalum nitride (TaN), nitrides of lanthanum series, ruthenium phosphide (RuxPy), nickel phosphide (NixPy), titanium carbide (TiC), zirconium carbide (ZrC), hafnium carbide (HfC), doped zinc oxide (ZnO), titanium mono oxide (TiO), hafnium mono oxide (HfO), zirconium mono oxide (ZrO), and tantalum carbide (TaC). 
     
     
         3 . The device of  claim 2 , further comprising a layer of metal in contact with and distinct from the transition layer. 
     
     
         4 . The device of  claim 3 , wherein the layer of elemental metal comprises titanium (Ti) or aluminum (Al). 
     
     
         5 . The device of  claim 1 , wherein the substrate is p-doped and the silicon source and drain regions comprise n-doped silicon, the device further comprising:
 a conducting material in contact with and distinct from the transition layer, and wherein the transition layer is selected from a group consisting of strontium oxide (SrO), barium sulfide (BaS), barium oxide (BaO), tantalum pentoxide (Ta2O5), zinc sulfide (ZnS), strontium sulfide (SrS), strontium titanate (SrTiO3), titanium dioxide (TiO2), tantalum nitride (Ta3N5), and barium titanate (BaTiO3).   
     
     
         6 . The device of  claim 1 , wherein the transition layer is selected from a group consisting of strontium titanate (SrTiO3) and barium titanate (BaTiO3). 
     
     
         7 . The device of  claim 1 , wherein the transition layer is less than two nanometers thick. 
     
     
         8 . The device of  claim 1 , wherein the substrate is n-doped and the silicon source and drain regions comprise p-doped silicon, the device further comprising:
 a conducting material in contact with and distinct from the transition layer, and wherein the transition layer is selected from a group consisting of strontium sulfide (SrS), zinc oxide (ZnO), and strontium oxide (SrO2).   
     
     
         9 . The device of  claim 8 , wherein the transition layer is less than two nanometers thick. 
     
     
         10 . A semiconductor device comprising:
 a substrate having a channel region therein;   a gate dielectric on the channel region;   a gate electrode on the gate dielectric;   a doped silicon source region and a doped silicon drain region, each adjacent the channel region such that the channel region is between the silicon source region and the silicon drain region;   a transition layer in contact with the silicon source region and the silicon drain region, wherein the transition layer comprises an insulator or a semiconducting material and includes no silicide region on the silicon source and drain regions; and   a conducting material in contact with and distinct from the transition layer;   wherein the transition layer has a thickness of 2 nanometers or less, such that the distance between the conducting material and the silicon source region is 2 nanometers or less and the distance between the conducting material and the silicon drain region is 2 nanometers or less.   
     
     
         11 . The device of  claim 10 , wherein the substrate is p-doped and the silicon source and drain regions comprise n-doped silicon, and the transition layer is selected from a group consisting of strontium oxide (SrO), barium sulfide (BaS), barium oxide (BaO), tantalum pentoxide (Ta2O5), zinc sulfide (ZnS), strontium sulfide (SrS), strontium titanate (SrTiO3), titanium dioxide (TiO2), tantalum nitride (Ta3N5), and barium titanate (BaTiO3). 
     
     
         12 . The device of  claim 10 , wherein the transition layer is selected from a group consisting of strontium titanate (SrTiO3) and barium titanate (BaTiO3). 
     
     
         13 . The device of  claim 10 , wherein the thickness of the transition layer is in the range of 0.1 to 1.0 nm. 
     
     
         14 . The device of  claim 10 , wherein the substrate is n-doped and the silicon source and drain regions comprise p-doped silicon, and the transition layer is selected from a group consisting of strontium sulfide (SrS), zinc oxide (ZnO), and strontium oxide (SrO2). 
     
     
         15 . The device of  claim 14 , wherein the thickness of the transition layer is in the range of 0.1 to 1.0 nm. 
     
     
         16 . The device of  claim 10 , wherein the device is a non-planar transistor device, such that the channel region, the source region, and the drain region are each at least one of in or on a silicon fin. 
     
     
         17 . A semiconductor device comprising:
 a p-doped substrate having a channel region therein;   a gate dielectric on the channel region;   a gate electrode on the gate dielectric;   an n-doped doped silicon source region and an n-doped doped silicon drain region, each adjacent the channel region such that the channel region is between the silicon source region and the silicon drain region; and   a transition layer in contact with the silicon source region and the silicon drain region, wherein the transition layer includes no silicide region on the silicon source region and no silicide region on the silicon drain region, wherein the transition layer is a conducting material and selected from a group consisting of titanium nitride (TiN), zirconium nitride (ZrN), hafnium nitride (HfN), tantalum nitride (TaN), nitrides of lanthanum series, ruthenium phosphide (RuxPy), nickel phosphide (NixPy), titanium carbide (TiC), zirconium carbide (ZrC), hafnium carbide (HfC), doped zinc oxide (ZnO), titanium mono oxide (TiO), hafnium mono oxide (HfO), zirconium mono oxide (ZrO), and tantalum carbide (TaC).   
     
     
         18 . The device of  claim 17 , wherein the transition layer is selected from a group consisting of titanium nitride (TiN), titanium carbide (TiC), titanium mono oxide (TiO), and tantalum carbide (TaC). 
     
     
         19 . The device of  claim 17 , further comprising a layer of metal in contact with and distinct from the transition layer. 
     
     
         20 . The device of  claim 17 , wherein the device is a non-planar transistor device, such that the channel region, the source region, and the drain region are each in or on a silicon fin extending from the substrate.