Nanowires for pillar interconnects

Abstract

An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may include a first set of pillars located on a first substrate. The semiconductor structure may include a second set of pillars located on a second substrate. The semiconductor structure may include a joining layer connecting the first pillar to the second pillar. The semiconductor structure may include an underfill layer located between the first and second substrate.

1 . A method of forming a semiconductor structure comprising:
 forming a plurality of first conductive pillars on a first substrate;   forming a plurality of conductive nanowires only on a first surface of the plurality of first conductive pillars, wherein the first surface is substantially parallel to a top surface of the first substrate, and wherein a material of the plurality of conductive nanowires is the same as a material of the first conductive pillars;   forming a plurality of second conductive pillars on a second substrate;   forming a solder bump on a second surface of the plurality of second conductive pillars; and   forming an electrical connection between the first pillar and the second pillar by joining the plurality of conductive nanowires with the solder bump.   
     
     
         2 . The method of  claim 1 , wherein forming a plurality of first conductive pillars comprises:
 forming a masking layer on a masked region of a first substrate, and wherein an unmasked region of the first substrate comprises a plurality of electrical connections;   forming a conductive material in the unmasked region, forming the plurality of first conductive pillars on the first substrate; and   removing the masking layer.   
     
     
         3 . The method of  claim 1 , wherein forming a plurality of conductive nanowires comprises:
 forming a porous layer on a surface of the plurality of first conductive pillars, wherein the porous layer comprises a plurality of pores extending from an exposed surface of the porous layer to the surface of the plurality of the first conductive pillars;   forming a conductive material in the plurality of pores; and   removing the porous layer.   
     
     
         4 . The method of  claim 3 , wherein the porous layer has a concentration of 4 pores/(μm) 2  to 400 pores/(μm) 2 . 
     
     
         5 . The method of  claim 1 , wherein forming an electrical connection between the first pillar and the second pillar comprises:
 aligning the plurality of conductive nanowires with the solder bump; and   performing thermal compression to join the plurality of conductive nanowires to the solder bump.   
     
     
         6 . The method of  claim 5 , wherein thermal compression is performed at a temperature of about 210° C. to about 250° C. 
     
     
         7 . The method of  claim 1 , further comprising depositing an underfill layer between the first substrate and the second substrate.