Trench confined epitaxially grown device layer(s)

Abstract

Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.

What is claimed is: 
     
         1 . A CMOS device disposed over a silicon substrate, the CMOS device comprising:
 a pMOS device having:
 a first source region and a first drain region with a Ge semiconductor channel disposed there between and disposed over a first planar semiconductor seeding surface having a composition other than that of the channel, the first planar semiconductor seeding surface being a top surface of 
 a first semiconductor mesa surrounded by isolation dielectric; and 
 a first gate dielectric layer and a first gate electrode layer disposed over the Ge semiconductor channel; and 
   an nMOS device having:
 a second source region and a second drain region with a III-V semiconductor channel disposed there between and disposed over a second planar semiconductor seeding surface having a composition other than that of the channel, the second planar semiconductor seeding surface being a top surface of a second semiconductor mesa surrounded by the isolation dielectric; and 
 a second gate dielectric layer and a second gate electrode layer disposed over the III-V semiconductor channel. 
   
     
     
         2 . The CMOS device of  claim 1 , wherein the Ge semiconductor channel has a top surface disposed a first distance from the seeding surface and the III-V semiconductor channel has a top surface disposed a second distance from the seeding surface, different the first distance. 
     
     
         3 . The CMOS device of  claim 1 , wherein a center the Ge semiconductor channel is aligned with a center of the first planar semiconductor seeding surface, and wherein a center the III-V semiconductor channel is aligned with a center of the second planar semiconductor seeding surface. 
     
     
         4 . The CMOS device of  claim 3 , wherein the first and second seeding surfaces are recessed below a top surface of the isolation dielectric. 
     
     
         5 . The CMOS device of  claim 1 , wherein the first and second gate dielectrics wrap-completely around surfaces of the semiconductor channels extending between the sources and drains. 
     
     
         6 . A method of fabricating a non-planar field effect transistor (FET) over a silicon substrate, the method comprising:
 forming a planar semiconductor seeding surface, the planar semiconductor seeding surface being a top surface of a semiconductor mesa on the silicon substrate and surrounded by isolation dielectric wherein the semiconductor mesa is a different semiconductor than the silicon substrate;   forming a source region and a drain region with a non-silicon semiconductor channel formed there between and over the planar semiconductor seeding surface, the planar semiconductor seeding surface having a composition other than that of the non-silicon semiconductor channel, wherein the non-silicon semiconductor channel is a III-V binary, ternary or quaternary compound semiconductor alloy; and   forming a gate dielectric layer and a gate electrode layer over the non-silicon semiconductor channel.   
     
     
         7 . The method of  claim 6 , wherein a center the channel is aligned with a center of the planar semiconductor seeding surface. 
     
     
         8 . The method of  claim 7 , wherein a bottom surface of the isolation dielectric is in contact with a semiconductor surface recessed below the seeding surface. 
     
     
         9 . The method of  claim 8 , wherein the seeding surface is recessed below a top surface of the dielectric isolation. 
     
     
         10 . The method of  claim 8 , wherein the non-silicon semiconductor channel is one layer of a semiconductor stack having a top surface disposed a distance from the seeding surface at least three times a minimum lateral dimension of the seeding surface. 
     
     
         11 . A non-planar field effect transistor (FET) disposed over a silicon substrate, the non-planar FET comprising:
 a source region and a drain region with a non-silicon semiconductor channel disposed there between and over a planar semiconductor seeding surface having a composition other than that of the non-silicon semiconductor channel, the planar semiconductor seeding surface being a top surface of a semiconductor mesa on the silicon substrate and disposed in a trench disposed in an isolation dielectric wherein the semiconductor mesa is a different semiconductor than the silicon substrate, and wherein the trench has a height to width aspect ratio of more than 4:1;   a gate dielectric layer and a gate electrode layer disposed over the non-silicon semiconductor channel.   
     
     
         12 . The non-planar FET of  claim 11 , wherein the non-silicon semiconductor channel is Ge, or a III-V binary ternary or quaternary compound semiconductor alloy, and wherein a center the channel is aligned with a center of the planar semiconductor seeding surface. 
     
     
         13 . The non-planar FET of  claim 12 , wherein a bottom surface of the isolation dielectric is in contact with a semiconductor surface recessed below the seeding surface. 
     
     
         14 . The non-planar FET of  claim 13 , wherein the seeding surface is recessed below a top surface of the dielectric isolation. 
     
     
         15 . The non-planar FET of  claim 13 , wherein the non-silicon semiconductor channel is one layer of a semiconductor stack having a top surface disposed a distance from the seeding surface at least three times a minimum lateral dimension of the seeding surface. 
     
     
         16 . A method of fabricating a non-planar field effect transistor (FET) over a silicon substrate, the method comprising:
 forming a planar semiconductor seeding surface, the planar semiconductor seeding surface being a top surface of a semiconductor mesa on the silicon substrate and surrounded by isolation dielectric wherein the semiconductor mesa is a different semiconductor than the silicon substrate, and wherein the trench has a height to width aspect ratio of more than 4:1;   forming a source region and a drain region with a non-silicon semiconductor channel formed there between and over the planar semiconductor seeding surface, the planar semiconductor seeding surface having a composition other than that of the non-silicon semiconductor channel; and   forming a gate dielectric layer and a gate electrode layer over the non-silicon semiconductor channel.   
     
     
         17 . The method of  claim 16 , wherein the non-silicon semiconductor channel is Ge, or a III-V binary ternary or quaternary compound semiconductor alloy, and wherein a center the channel is aligned with a center of the planar semiconductor seeding surface. 
     
     
         18 . The method of  claim 17 , wherein a bottom surface of the isolation dielectric is in contact with a semiconductor surface recessed below the seeding surface. 
     
     
         19 . The method of  claim 18 , wherein the seeding surface is recessed below a top surface of the dielectric isolation. 
     
     
         20 . The method of  claim 18 , wherein the non-silicon semiconductor channel is one layer of a semiconductor stack having a top surface disposed a distance from the seeding surface at least three times a minimum lateral dimension of the seeding surface.