Semiconductor process

Abstract

A semiconductor structure includes at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source/drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source/drain region. Additionally, a semiconductor process formed said semiconductor structure is also provided.

What is claimed is: 
     
         1 . A semiconductor process, comprising:
 providing a substrate;   forming a MOS transistor on the substrate, wherein the MOS transistor comprises a gate located on the substrate and a source/drain region located in the substrate next to the gate;   forming an interdielectric layer covering the substrate next to the gate;   forming a plurality of contact holes in the interdielectric layer and exposing at least a part of the source/drain region;   respectively forming an epitaxial structure in each of the contact holes, directly contacting and only located on the source/drain region;   forming a silicide on the epitaxial structure in each of the contact holes;   depositing a dielectric layer on the interdielectric layer and covering the gate;   forming a plurality of corresponding contact holes in the dielectric layer and connecting the contact holes; and   respectively filling a metal material into each of the contact holes and the corresponding contact holes and on the silicide.   
     
     
         2 . The semiconductor process according to  claim 1 , wherein the gate comprises a polysilicon gate. 
     
     
         3 . The semiconductor process according to  claim 1 , wherein the gate comprises a sacrificial gate, and further comprising:
 replacing the sacrificial gate with a metal gate after the interdielectric layer covering the substrate next to the gate is formed.   
     
     
         4 . The semiconductor process according to  claim 1 , further comprising:
 forming a contact etch stop layer between the substrate and the interdielectric layer before the interdielectric layer covering the substrate next to the gate is formed.   
     
     
         5 . The semiconductor process according to  claim 1 , wherein the substrate comprises a bulk substrate. 
     
     
         6 . The semiconductor process according to  claim 1 , wherein the substrate comprises a bottom substrate and at least a fin-shaped structure on the bottom substrate, and the gate and the source/drain region are formed on the fin-shaped structure. 
     
     
         7 . The semiconductor process according to  claim 1 , wherein the numbers of the MOS transistor are more than one, and the MOS transistors are distributed to form a static random access memory (SRAM). 
     
     
         8 . The semiconductor process according to  claim 1 , wherein the epitaxial structure comprises a strained epitaxial silicon. 
     
     
         9 . The semiconductor process according to  claim 1 , wherein respectively forming the epitaxial structure in each of the contact holes comprises respectively forming the epitaxial structure to fill up each of the contact holes. 
     
     
         10 . The semiconductor process according to  claim 1 , wherein respectively forming the epitaxial structure in each of the contact holes comprises respectively forming the epitaxial structure to fill part of each of the contact holes. 
     
     
         11 . The semiconductor process according to  claim 1 , further comprising:
 forming a gate contact hole in the dielectric layer to expose the gate while forming the plurality of corresponding contact holes in the dielectric layer.   
     
     
         12 . A semiconductor process, comprising:
 providing a substrate;   forming a MOS transistor on the substrate, wherein the MOS transistor comprises a gate located on the substrate and a source/drain region located on the substrate next to the gate;   sequentially forming an interdielectric layer and a dielectric layer covering the gate and the substrate;   forming a plurality of contact holes in the interdielectric layer and the dielectric layer to expose at least a part of the source/drain region;   respectively forming an epitaxial structure in each of the contact holes;   respectively forming a silicide on the epitaxial structure in each of the contact holes; and   respectively filling a metal material into each of the contact holes and on the silicide.   
     
     
         13 . The semiconductor process according to  claim 12 , wherein the gate comprises a polysilicon gate. 
     
     
         14 . The semiconductor process according to  claim 12 , wherein the gate comprises a sacrificial gate, and the steps of sequentially forming an interdielectric layer and a dielectric layer covering the gate and the substrate comprise:
 forming the interdielectric layer on the substrate next to the sacrificial gate;   replacing the sacrificial gate with a metal gate; and   forming the dielectric layer on the interdielectric layer and covering the metal gate.   
     
     
         15 . The semiconductor process according to  claim 12 , further comprising:
 forming a contact etch stop layer between the substrate and the interdielectric layer before the interdielectric layer and the dielectric layer covering the gate and the substrate are sequentially formed.   
     
     
         16 . The semiconductor process according to  claim 12 , wherein the substrate comprises a bulk substrate. 
     
     
         17 . The semiconductor process according to  claim 12 , wherein the substrate comprises a bottom substrate and at least a fin-shaped structure located on the bottom substrate, and the gate and the source/drain region are formed on the fin-shaped structure. 
     
     
         18 . The semiconductor process according to  claim 12 , wherein the numbers of the MOS transistor are more than one, and the MOS transistors are distributed to forma static random access memory (SRAM). 
     
     
         19 . The semiconductor process according to  claim 12 , wherein the epitaxial structure comprises a strained epitaxial silicon. 
     
     
         20 . The semiconductor process according to  claim 12 , wherein respectively forming the epitaxial structure in each of the contact holes comprises respectively forming the epitaxial structure to fill up each of the contact holes. 
     
     
         21 . The semiconductor process according to  claim 12 , wherein respectively forming the epitaxial structure in each of the contact holes comprises respectively forming the epitaxial structure to fill part of each of the contact holes. 
     
     
         22 . The semiconductor process according to  claim 12 , further comprising:
 forming a gate contact hole in the dielectric layer to expose the gate while forming the plurality of contact holes.