Refresh method for flash memory and related memory controller thereof

Abstract

A refresh method for a flash memory includes at least the following steps: performing a write operation to store an input data into a storage space in the flash memory; checking reliability of the storage space with the input data already stored therein; and when the reliability of the storage space meets a predetermined criterion, performing a refresh operation upon the storage space based on the input data. For example, the write operation stores the input data into the storage space through an initial program operation and at least one reprogram operation following the initial program operation; and the refresh operation is an additional reprogram operation applied to the storage space for programming the input data recovered from the storage space into original storage locations in the storage space.

What is claimed is: 
     
         1 . A refresh method for a flash memory, comprising:
 performing a write operation to store an input data into a storage space in the flash memory, the write operation comprising an initial program operation and at least one reprogram operation which are sequentially performed;   checking reliability of the storage space with the input data already stored therein; and   when the reliability of the storage space meets a predetermined criterion:
 recovering the input data from the storage space; and 
 programming the input data recovered from the storage space into original storage locations in the storage space, the programming step being an additional reprogram operation applied to the storage space and different and distinct from the initial program operation and the at least one reprogram operation. 
   
     
     
         2 . The refresh method of  claim 1 , wherein the step of checking the reliability of the storage space comprises:
 detecting if the storage space with the input data already stored therein suffers from data-retention disturbance;   wherein the additional reprogram operation applied to the storage space is performed when the storage space with the input data already stored therein suffers from the data-retention disturbance.   
     
     
         3 . The refresh method of  claim 2 , wherein the at least one reprogram operation comprises a first reprogram operation and a second reprogram operation following the first reprogram operation. 
     
     
         4 . The refresh method of  claim 1 , wherein the storage space is composed of a plurality of N-bit multi-level cells, and N is a positive value greater than two. 
     
     
         5 . The refresh method of  claim 1 , wherein the input data stored in the storage space by the write operation is read based on a first initial setting of reference threshold voltage values, and the input data stored in the storage space processed by the recovering and programing steps is read based on a second initial setting of reference threshold voltage values different from the first initial setting of reference threshold voltage values. 
     
     
         6 . The refresh method of  claim 5 , wherein a highest reference threshold voltage value defined in the second initial setting of reference threshold voltage values is greater than a highest reference threshold voltage value defined in the first reference threshold voltage values. 
     
     
         7 . The refresh method of  claim 5 , further comprising:
 after performing the additional reprogramming operation upon the storage space, storing an indicator indicative of the second initial setting of reference threshold voltage values.   
     
     
         8 . The refresh method of  claim 1 , wherein the storage space is a portion of a block of the flash memory. 
     
     
         9 . The refresh method of  claim 8 , further comprising:
 when the reliability of the storage space meets the predetermined criterion, performing the recovering step and programming step upon a remaining portion of the block of the flash memory.   
     
     
         10 . A memory controller of a flash memory, comprising:
 a write circuit, coupled to the flash memory, the write circuit arranged to store an input data into a storage space in the flash memory, the write operation comprising an initial program operation and at least one reprogram operation which are sequentially performed;   a check circuit, arranged to check reliability of the storage space with the input data already stored therein; and   a refresh circuit, coupled to the check circuit and the flash memory; when the reliability of the storage space meets a predetermined criterion, the refresh circuit arranged for:
 recovering the input data from the storage space; and 
 programming the input data recovered from the storage space into original storage locations in the storage space, the programming step being an additional reprogram operation applied to the storage space and different and distinct from the initial program operation and the at least one reprogram operation. 
   
     
     
         11 . The memory controller of  claim 10 , wherein the check circuit checks the reliability of the storage space by detecting if the storage space with the input data already stored therein suffers from data-retention disturbance; and, the additional reprogram operation applied to the storage space is performed when the storage space with the input data already stored therein suffers from the data-retention disturbance. 
     
     
         12 . The memory controller of  claim 11 , wherein the at least one reprogram operation comprises a first reprogram operation and a second reprogram operation following the first reprogram operation. 
     
     
         13 . The memory controller of  claim 10 , wherein the storage space accessed by the memory controller is composed of a plurality of N-bit multi-level cells, and N is a positive value greater than two. 
     
     
         14 . The memory controller of  claim 10 , wherein the input data stored in the storage space by the write circuit is read based on a first initial setting of reference threshold voltage values, and the input data stored in the storage space processed by the refresh circuit is read based on a second initial setting of reference threshold voltage values different from the first initial setting of reference threshold voltage values. 
     
     
         15 . The memory controller of  claim 14 , wherein a highest reference threshold voltage value defined in the second initial setting of reference threshold voltage values is greater than a highest reference threshold voltage value defined in the first initial setting of reference threshold voltage values. 
     
     
         16 . The memory controller of  claim 14 , wherein after refreshing the storage space, the refresh circuit stores an indicator indicative of the second initial setting of reference threshold voltage values. 
     
     
         17 . The memory controller of  claim 10 , wherein the storage space accessed by the memory controller is a portion of a block of the flash memory. 
     
     
         18 . The memory controller of  claim 17 , wherein the refresh circuit is further arranged to performing the recovering step and programming step upon a remaining portion of the block of the flash memory when the reliability of the storage space meets the predetermined criterion.