US2017155529A1PendingUtilityA1

Clock Data Recovery Circuitry Associated With Programmable Logic Device Circuitry

Assignee: ALTERA CORPPriority: Mar 14, 2000Filed: Dec 12, 2016Published: Jun 1, 2017
Est. expiryMar 14, 2020(expired)· nominal 20-yr term from priority
H03L 7/089H04L 7/0337G11C 7/222H04L 7/033H03L 7/07H04L 7/0025H04L 7/02H04L 25/0228H03L 7/199H03M 9/00H03L 7/187H03L 7/0891H03L 7/0995G11C 7/22H03L 7/0802H04L 25/03273H03L 7/0814
44
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.

Claims

exact text as granted — not AI-modified
1 .- 17 . (canceled) 
     
     
         18 . A method for recovering clock information from a data signal, comprising:
 producing, using first circuitry, candidate recovered clock signals from a reference clock signal; and   producing, using second circuitry, a recovered clock signal by making a selection from the candidate recovered clock signals of at least one signal based on a comparison of proximity between transitions in the recovered clock signal and transitions in the data signal, compensated fro static skew between the data signal and the reference clock signal, and maintaining the selection during an absence of data signal transitions, the producing comprising:
 determining the static skew based on a received training pattern configured to allow the second circuitry to determine and compensate for the static skew, wherein:
 the second circuitry is unlimited run-length compatible, and wherein the comparison of the proximity between the transitions in the recovered clock signal and the transitions in the data signal comprises:
 a comparison between the data signal and the recovered clock signal triggered by a rising edge transition in the data signal independent of the recovered clock signal, and 
 a comparison between the data signal and the recovered clock signal triggered by a falling edge transition in the data signal independent of the recovered clock signal.

Join the waitlist — get patent alerts

Track US2017155529A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.