Integrated tensile strained silicon nfet and compressive strained silicon-germanium pfet implemented in finfet technology

Abstract

A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 a substrate including a first area and a second area;   a plurality of tensile strained silicon semiconductor fins in the first area of the substrate;   a plurality of compressive strained silicon-germanium semiconductor fins in the second area of the substrate, wherein said plurality of compressive strained silicon-germanium semiconductor fins comprise tensile strained silicon semiconductor material modified to relax tensile strain and include germanium;   a first metal gate extending over the plurality of tensile strained silicon semiconductor fins in the first area; and   a second metal gate extending over the plurality of compressive strained silicon-germanium semiconductor fins in the second area.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the substrate is a silicon on insulator type substrate. 
     
     
         3 . The integrated circuit of  claim 1 , wherein:
 the tensile strained silicon semiconductor fins and first metal gate form finFET transistors of a first conductivity type; and   the compressive strained silicon-germanium semiconductor fins and second metal gate form finFET transistors of a second conductivity type.   
     
     
         4 . The integrated circuit of  claim 3 , wherein the first conductivity type is n-type and the second conductivity type is p-type. 
     
     
         5 . An integrated circuit, comprising:
 a substrate including a first area and a second area;   a first plurality of semiconductor fins in the first area of the substrate;   a second plurality of semiconductor fins in the second area of the substrate;   wherein the first and second pluralities of semiconductor fins are formed from a layer of silicon semiconductor material that is tensile strained and patterned to define the first and second pluralities of semiconductor fins; and   wherein the silicon semiconductor material of the second plurality of semiconductor fins has relaxed tensile strain in comparison to the silicon semiconductor material of the first plurality of semiconductor fins and further includes germanium which is not present in the first plurality of semiconductor fins;   a first metal gate extending over the first plurality of semiconductor fins in the first area; and   a second metal gate extending over the second plurality of semiconductor fins in the second area.   
     
     
         6 . The integrated circuit of  claim 5 , wherein the substrate is a silicon on insulator type substrate and the layer of silicon semiconductor material is a top layer of said silicon on insulator type substrate. 
     
     
         7 . The integrated circuit of  claim 5 , wherein:
 the first plurality of semiconductor fins and first metal gate form finFET transistors of a first conductivity type; and   the second plurality of semiconductor fins and second metal gate form finFET transistors of a second conductivity type.   
     
     
         8 . The integrated circuit of  claim 7 , wherein the first conductivity type is n-type and the second conductivity type is p-type. 
     
     
         9 . An integrated circuit, comprising:
 a substrate including a first area and a second area;   a plurality of tensile strained silicon semiconductor fins in the first area of the substrate;   a plurality of compressive strained silicon-germanium semiconductor fins in the second area of the substrate;   a first metal gate extending over the plurality of tensile strained silicon semiconductor fins in the first area; and   a second metal gate extending over the plurality of compressive strained silicon-germanium semiconductor fins in the second area.   
     
     
         10 . The integrated circuit of  claim 9 , wherein the substrate is a silicon on insulator type substrate. 
     
     
         11 . The integrated circuit of  claim 9 , wherein:
 the tensile strained silicon semiconductor fins and first metal gate form finFET transistors of a first conductivity type; and   the compressive strained silicon-germanium semiconductor fins and second metal gate form finFET transistors of a second conductivity type.   
     
     
         12 . The integrated circuit of  claim 11 , wherein the first conductivity type is n-type and the second conductivity type is p-type.