Information processing apparatus and method for generating coupling information

Abstract

A processing apparatus includes a memory, and a processor coupled to the memory and configured to acquire first data that indicates correspondence relationship between a first address given to a first adapter of a first device and a first bus number given to a first bus coupled to the first adapter, acquire second data that indicates correspondence relationship between a second address given to a second adapter of a first device and a second bus number given to a second bus coupled to the second adapter, acquire third data that indicates correspondence relationship between the first address and a port number given to a port of a second device, the port being coupled to the first adapter with the first bus, and when the second bus number is identical to the first bus number, generate fourth data that indicates that the second adapter is coupled to the port.

What is claimed is: 
     
         1 . A processing apparatus comprising:
 a memory; and   a processor that is coupled to the memory and configured to:   store a first address of a first logical adapter of a first device in association with a port number of a port of a second device, and   store a second address of a second logical adapter of the first device in association with the port number of the port of the second device, wherein   the first logical adapter and the second logical adapter is included in a first physical adapter,   the first physical adapter is coupled to the port with a bus, and   a first virtual machine in the first device is accessible to the port via the first logical adapter and the bus, and a second virtual machine in the first device is accessible to the port via the second logical adapter and the bus.   
     
     
         2 . The processing apparatus of  claim 1 , wherein the second device does not acknowledge that the port is accessible to the second logical adapter via the bus. 
     
     
         3 . The processing apparatus of  claim 1 ,
 wherein the processor is configured to:
 retrieve a first MAC address as the first address of the first logical adapter from the first device, and 
 retrieve a second MAC address as the second address of the second logical adapter from the first device. 
   
     
     
         4 . The processing apparatus of  claim 1 ,
 wherein the processor is configured to:
 retrieve the first address of the first logical adapter from the second device, and 
 retrieve the second address of the second adapter from the first device. 
   
     
     
         5 . The processing apparatus of  claim 1 ,
 wherein the processor is configured to:
 retrieve, from the first device, first information indicating that both of the first logical adapter and the second logical adapter are coupled with the bus, and 
 retrieve, from the second device, second information indicating that the first logical adapter is accessible to the port via the bus. 
   
     
     
         6 . The processing apparatus of  claim 1 , wherein
 the processor is configured to ping the second device using a third address of a third logical adapter to determine if the third address of the third logical adapter is already registered in the memory, wherein the third logical adapter is part of a second physical adapter than the first physical adapter, but is coupled to the bus.   
     
     
         7 . A method executed by a computer, the method comprising:
 storing a first address of a first logical adapter of a first device in association with a port number of a port of a second device, and   storing a second address of a second logical adapter of the first device in association with the port number of the port of the second device, wherein
 the first logical adapter and the second logical adapter is included in a first physical adapter, 
 the first physical adapter is coupled to the port with a bus, and 
 a first virtual machine in the first device is accessible to the port via the first logical adapter and the bus, and a second virtual machine in the first device is accessible to the port via the second logical adapter and the bus. 
   
     
     
         8 . The method according to  claim 7 , wherein the second device does not acknowledge that the port is accessible to the second logical adapter via the bus. 
     
     
         9 . The method according to  claim 7 , further comprising:
 retrieving a first MAC address as the first address of the first logical adapter from the first device, and   retrieving a second MAC address as the second address of the second logical adapter from the first device.   
     
     
         10 . The method according to  claim 7 , further comprising:
 retrieving the first address of the first logical adapter from the second device, and   retrieving the second address of the second adapter from the first device.   
     
     
         11 . The method according to  claim 7 , further comprising:
 retrieving, from the first device, first information indicating that both of the first logical adapter and the second logical adapter are coupled with the bus, and   retrieving, from the second device, second information indicating that the first logical adapter is accessible to the port via the bus.   
     
     
         12 . The method according to  claim 7 , further comprising:
 the processor is configured to ping the second device using a third address of a third logical adapter to determine if the third address of the third logical adapter is already registered in the memory, wherein the third logical adapter is part of a second physical adapter than the first physical adapter, but is coupled to the bus.