Verifying communication lanes by individually disconnecting transmit wires by wire polarity

Abstract

Individual wire defects in a data transfer/communication system that employs differential signaling can be detected during connectivity verification of a link prior to link training by individually disconnecting wires by wire polarity and testing the link. For example, the positive transmit wire of a lane may be verified by disconnecting the negative transmit wire of the lane and performing link connectivity verification. If the link passes connectivity verification, then the positive transmit wire of the lane is functioning normally. Connectivity of the negative transmit wire of the lane may then be verified by disconnecting the positive transmit wire of the lane and determining if the passes the connectivity verification

What is claimed is: 
     
         1 . A method comprising:
 disconnecting, by a computing device, functionally each of a plurality of transmit wires using their corresponding at least one in-line switch, wherein each of the plurality of transmit wires includes a first transmit wire of a first polarity and a second transmit wire of a second polarity, and providing the first transmit wire and the second transmit wire in one of a plurality of full duplex channels; and   controlling, by a computing device, activation of the at least one in-line switch to functionally disconnect all of the transmit wires of a first polarity for a first receive detection, and deactivation of the at least one in-line switch after the first receive detection, to functionally disconnect all of the transmit wires of a second polarity for a second receive detection.   
     
     
         2 . The method of  claim 1 , further comprising providing a printed circuit board, wherein the printed circuit board comprises the at least one in-line switch. 
     
     
         3 . The method of  claim 1 , further comprising providing an integrated circuit having a transmit circuitry and a receive circuitry, wherein the transmit circuitry comprises a transmitter and the receive circuitry comprises a receiver; and the transmit circuitry is coupled to the plurality of full duplex channels. 
     
     
         4 . The method of  claim 3 , further comprising wherein the provided integrated circuit further comprises the at least one in-line switch. 
     
     
         5 . The method of  claim 3 , further comprising providing a second integrated circuit coupled to the integrated circuit via the plurality of full duplex channels, wherein each of the plurality of duplex channels includes a first receive wire of the first polarity and a second receive wire of the second polarity, each of the receive wires having the at least one in-line switch to functionally disconnect the corresponding wire, wherein the second integrated circuit is coupled to control the at least one in-line switch of the receive wires. 
     
     
         6 . The method of  claim 1 , further comprising providing a serial computer bus interface to control the at least one in-line switch and providing a data link layer component that controls activation of the at least one in-line switch, wherein the data link layer component comprises at least one component that is coupled to supply a control signal or control data to a serial computer bus interface. 
     
     
         7 . A non-transitory machine readable medium having stored thereon instructions for performing a method comprising machine executable code which when executed by at least one machine, causes the machine to:
 disconnect functionally each of a plurality of transmit wires using their corresponding at least one in-line switch, wherein each of the plurality of transmit wires includes a first transmit wire of a first polarity and a second transmit wire of a second polarity, and one of a plurality of full duplex channels including the first transmit wire and the second transmit wire; and   control activation of the at least one in-line switch to functionally disconnect all of the transmit wires of a first polarity for a first receive detection, and deactivation of the at least one in-line switch after the first receive detection, to functionally disconnect all of the transmit wires of a second polarity for a second receive detection.   
     
     
         8 . The non-transitory machine readable medium as set forth in  claim 7 , further comprising machine executable code which when executed by at least one machine, causes the machine to:
 functionally disconnect each of a first receive wire of the first polarity and a second receive wire of the second polarity included in each of the plurality of duplex channels by using their corresponding at least one in-line switch, and controlling the at least one in-line switch of the receive wires.   
     
     
         9 . The non-transitory machine readable medium as set forth in  claim 7 , further comprising machine executable code which when executed by at least one machine, causes the machine to:
 control activation of the at least one in-line switch by providing a data link layer component;   control the at least one in-line switch by a serial computer bus interface; and   supply a control signal or control data to the serial computer bus interface by coupling at least one component of the data link layer component.   
     
     
         10 . A computing device comprising:
 a memory containing machine readable medium comprising machine executable code having stored thereon instructions for performing a method of functionally disconnecting wires by activation of switches; and   a processor coupled to the memory, the processor configured to execute the machine executable code to cause the processor to:
 activate first switches in each full duplex channel of a link coupling integrated circuits, wherein each full duplex channel includes a pair of transmit wires and a pair of receive wires, each pair of wires having a first wire of a first polarity and a second wire of a second polarity for differential signaling, the first switches are in the first wires of the transmit wires, and the activation of the first switches functionally disconnects the first wires; 
 initiate a first receive detection on the link; 
 associate a failure in the first receive detection with the second polarity; 
 deactivate the first switches; 
 activate second switches in each full duplex channel of the link, wherein the second switches are in the second wires of the transmit wires and the activation of the second switches functionally disconnects the second wires; 
 initiate a second receive detection on the link; and 
 associate a failure in the second receive detection with the first polarity. 
   
     
     
         11 . The device of  claim 10 , wherein the processor is further configured to execute the machine executable code to cause the processor to:
 at least one of supply a control signal to the first switches or set a control value.   
     
     
         12 . The device of  claim 10 , wherein the processor is further configured to execute the machine executable code to cause the processor to:
 supply pulses over the pair of transmit wires in each full duplex channel.   
     
     
         13 . The device of  claim 10 , wherein the processor is further configured to execute the machine executable code to cause the processor to:
 indicate a defect with the second wire of the second polarity in the full duplex channel that caused the failure.   
     
     
         14 . The device of  claim 10 , wherein the processor is further configured to execute the machine executable code to cause the processor to:
 indicate a defect with the first wire of the first polarity in the full duplex channel that caused the failure.   
     
     
         15 . The device of  claim 10 , wherein the processor is further configured to execute the machine executable code to cause the processor to:
 determine that the first receive detection had a failure; and   iteratively conduct receive detection on each full duplex channel of the link.   
     
     
         16 . The device of  claim 10 , wherein the processor is further configured to execute the machine executable code to cause the processor to:
 conduct receive detection on all channels of the link.   
     
     
         17 . The device of  claim 10 , wherein the processor is further configured to execute the machine executable code to cause the processor to:
 terminate link training if either of the first receive detection and the second receive detection had a failure and proceed with link training if neither of the first receive detection and the second receive detection had a failure.