Semiconductor apparatus and method for fabricating the same

Abstract

A method for fabricating a semiconductor apparatus includes providing a semiconductor substrate, stacking a conductive layer, a variable resistance layer, and a sacrificial layer on the semiconductor substrate, etching the conductive layer, the variable resistance layer, and the sacrificial layer to form a pillar structure including a lower electrode, a variable resistor device, and a sacrificial layer pattern, removing the sacrificial layer pattern, and forming an upper electrode over the variable resistor device in a hole which is formed by removing the sacrificial layer pattern.

What is claimed is: 
     
         1 . A semiconductor apparatus comprising:
 a semiconductor substrate;   a lower electrode formed over the semiconductor substrate;   a variable resistor device formed over the lower electrode;   an upper electrode formed over the variable resistor device;   a spacer, which reduces a contact area between the variable resistor device and the upper electrode by narrowing down a bottom area of the upper electrode, formed over an outer sidewall of a lower portion of the upper electrode; and   an intercell insulating layer formed between structures each of which has the lower electrode, the variable resistor device, the spacer and the upper electrode,   wherein a contact area between the variable resistor device and the upper electrode is smaller than an upper surface area of the variable resistor device.   
     
     
         2 . The semiconductor apparatus of  claim 1 , further comprising:
 a protection layer pattern suitable to protect the variable resistor device and provided between the variable resistor device and the spacer.   
     
     
         3 . The semiconductor apparatus of  claim 1 , further comprising:
 a capping layer formed over outer sidewalls of the intercell insulating layer.   
     
     
         4 . The semiconductor apparatus of  claim 1 , wherein an upper surface of the intercell insulating layer and an upper surface of the upper electrode are coplanar.