Perfectly shaped controlled nanowires

Abstract

A fin stack structure is provided on an insulator layer. The fin stack structure comprises, from bottom to top, a first semiconductor fin portion, a dielectric fin portion, a second semiconductor fin portion and a hard mask fin portion. A sacrificial gate structure is formed on a portion of the fin stack structure. The hard mask fin portion and the dielectric fin portion not located beneath the sacrificial gate structure are removed. An epitaxial semiconductor material structure is then formed from exposed surfaces of each semiconductor fin portion. The sacrificial gate structure is then removed. Next, remaining portions of the hard mask fin portion and the dielectric fin portion are removed. The insulating layer is then recessed. After recessing the insulator layer, the first and second semiconductor fin portions are suspended and are stacked one atop the other.

1 . A semiconductor structure comprising:
 a stack of suspended semiconductor nanowires located above a surface of an insulator layer, wherein each semiconductor nanowire of said stack has a same shape and dimension; and   a functional gate structure wrapping around each suspended semiconductor nanowire of said stack, wherein an entirety of a bottommost surface of said functional gate structure is in direct physically contact with said surface of said insulator layer.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein each semiconductor nanowire comprises a same semiconductor material. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein at least one semiconductor nanowire of said stack comprises a semiconductor material that differs from remaining semiconductor nanowires of said stack. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein said functional gate structure comprises a gate dielectric portion and a gate conductor portion, wherein said gate dielectric portion is present entirely around each semiconductor nanowire of said stack. 
     
     
         5 . The semiconductor structure of  claim 4 , wherein said insulator layer has a topmost surface contacting a portion of said gate conductor portion of said functional gate structure and a bottommost surface contacting a topmost surface of a handle substrate. 
     
     
         6 . The semiconductor structure of  claim 1 , further comprising an epitaxial semiconductor structure located on opposites sides of said functional gate structure. 
     
     
         7 . The semiconductor structure of  claim 1 , wherein a first suspended semiconductor nanowire of said stack of suspended semiconductor nanowires comprises a first semiconductor material, a second suspended semiconductor nanowire of said stack of suspended semiconductor nanowires comprises a second semiconductor material, and a third suspended semiconductor nanowire of said stack of suspended semiconductor nanowires comprises a third semiconductor material, wherein said third semiconductor material is different from at least one of said first semiconductor material and said second semiconductor material. 
     
     
         8 . The semiconductor structure of  claim 1 , wherein at least one of said suspended semiconductor nanowires of said stack of suspended semiconductor nanowires comprises a III-V compound semiconductor or a silicon germanium alloy. 
     
     
         9 . The semiconductor structure of  claim 1 , wherein each suspended semiconductor nanowire of said stack of suspended semiconductor nanowires has sidewall surfaces that are vertically aligned to each other. 
     
     
         10 . The semiconductor structure of  claim 1 , wherein each suspended semiconductor nanowire has non-rounded surfaces. 
     
     
         11 . A semiconductor structure comprising:
 a plurality of vertically stacked and suspended semiconductor nanowires present above an insulator layer, wherein each semiconductor nanowire of said plurality of vertically stacked and suspended semiconductor nanowires has a same shape and dimension; and   a functional gate structure wrapping around each suspended semiconductor nanowire of said plurality of vertically stacked and suspended semiconductor nanowires, wherein an entirety of a bottommost surface of said functional gate structure is in direct physically contact with a surface of said insulator layer.   
     
     
         12 . The semiconductor structure of  claim 11 , wherein each vertically stacked and suspended semiconductor nanowire is separated from its nearest neighboring vertically stacked and suspended semiconductor nanowire by a pitch from 20 nm to 50 nm. 
     
     
         13 . The semiconductor structure of  claim 12 , wherein each suspended semiconductor nanowire of said plurality of vertically stacked and suspended semiconductor nanowires has sidewall surfaces that are vertically aligned to each other. 
     
     
         14 . The semiconductor structure of  claim 13 , wherein each suspended semiconductor nanowire has non-rounded surfaces. 
     
     
         15 . The semiconductor structure of  claim 11 , wherein each suspended semiconductor nanowire within one of said plurality of vertically stacked and suspended semiconductor nanowires comprises a different semiconductor material. 
     
     
         16 . The semiconductor structure of  claim 11 , wherein each suspended semiconductor nanowire of said plurality of vertically stacked and suspended semiconductor nanowires comprises a same semiconductor material. 
     
     
         17 . The semiconductor structure of  claim 1 , further comprising a handle substrate located entirely beneath a bottommost surface of said insulator layer. 
     
     
         18 . The semiconductor structure of  claim 17 , wherein said handle substrate comprises a semiconductor material.