Normally-off transistor with reduced on-state resistance and manufacturing method

Abstract

A normally-off electronic device, comprising: a semiconductor body including a heterostructure that extends over a buffer layer; a recessed-gate electrode, extending in a direction orthogonal to the plane; a first working electrode and a second working electrode at respective sides of the gate electrode; and an active area housing, in the on state, a conductive path for a flow of electric current between the first and second working electrodes. A resistive region extends at least in part in the active area that is in the buffer layer and is designed to inhibit the flow of current between the first and second working electrodes when the device is in the off state. The gate electrode extends in the semiconductor body to a depth at least equal to the maximum depth reached by the resistive region.

1 . A normally-off electronic device, comprising:
 a semiconductor body lying in a plane and including a buffer region and a heterostructure extending over the buffer region;   a gate recessed electrode extending in the semiconductor body at least partially through the buffer region, along a direction orthogonal to said plane;   a first working electrode and a second working electrode, which extend at respective sides of the gate electrode; and   an active area which extends in the buffer region alongside and underneath the gate electrode and is configured to house, in a first operating condition in which a voltage between the gate electrode and the first working electrode is higher than a threshold voltage, a conductive path for a flow of an electric current between the first and second working electrodes, wherein:   said active area in the buffer region houses a resistive region configured to hinder, in a second operating condition in which the voltage between the gate electrode and the first working electrode is lower than the threshold voltage, the electric current flow between the first and second working electrodes, and   the resistive region extends at least in part in said active area, and said gate electrode extends in the semiconductor body to a depth, in said direction, equal to, or greater than, a maximum depth reached by the resistive region.   
     
     
         2 . The normally-off electronic device according to  claim 1 , wherein said heterostructure comprises a channel layer, of a material that is a compound formed by elements of Groups III-V including nitride, and an electron-supply layer extending over the channel layer. 
     
     
         3 . The normally-off electronic device according to  claim 1 , wherein the resistive region is an implanted region of the heterostructure and extends between the gate electrode and at least one of the first working electrode and the second working electrode. 
     
     
         4 . The normally-off electronic device according to  claim 3 , wherein the resistive region has a density of dopant species comprised between 10 15  ions/cm 3  and 10 20  ions/cm 3 . 
     
     
         5 . The normally-off electronic device according to  claim 1 , wherein the resistive region is a layer of a compound formed by elements of Groups III-V with a doping of a P-type, extending underneath the heterostructure. 
     
     
         6 . The normally-off electronic device according to  claim 1 , wherein:
 the semiconductor body includes a semiconductor substrate;   the buffer region extends over the substrate and includes an electrical-conduction layer of a compound formed by elements of Groups III-V of an intrinsic type or with N-type doping;   said resistive region extends on the electrical-conduction layer; and   said gate electrode extends in the semiconductor body at least to the electrical-conduction layer.   
     
     
         7 . The normally-off electronic device according to  claim 1 , wherein:
 the semiconductor body includes a semiconductor substrate; and an interface layer of a compound formed by elements of Groups III-V and extending between the substrate and the buffer region, and   said gate electrode extends in the semiconductor body at least to the interface layer.   
     
     
         8 . A method for manufacturing a normally-off electronic device, comprising:
 forming a recessed gate electrode in a semiconductor body extending in a plane and including a buffer region and a heterostructure extending over the buffer region, the gate electrode extending at least partially through the buffer region, along a direction orthogonal to said plane;   forming a first working electrode and a second working electrode at respective sides of the gate electrode, wherein the gate electrode, and the first and second working electrodes define an active area in the buffer region alongside and underneath the gate electrode, said active area being configured to house, in a first operating condition in which a voltage between the gate electrode and the first working electrode is higher than a threshold voltage, a conductive path for a flow of electric current between the first and second working electrodes; and   forming a resistive region at least in part in the active area in said buffer region, said gate electrode extending in the semiconductor body as far as a depth, in said direction, equal to, or higher than, a maximum depth reached by the resistive region, the resistive region being configured to hinder, in a second operating condition in which the voltage between the gate electrode and the first working electrode is lower than the threshold voltage, the flow of electric current between the first and second working electrodes.   
     
     
         9 . The method according to  claim 8 , wherein forming the heterostructure comprises forming a channel layer of a material that is a compound formed by elements of Groups III-V including nitride, and forming an electron-supply layer on the channel layer. 
     
     
         10 . The method according to  claim 8 , wherein forming the resistive region includes implanting dopant species of a P-type in the heterostructure and between the gate electrode and at least one of the first working electrode and the second working electrode. 
     
     
         11 . The method according to  claim 10 , wherein forming the resistive region includes depositing a layer of a compound formed by elements of Groups III-V with a doping of a P-type, underneath the heterostructure. 
     
     
         12 . The method according to  claim 8 , wherein:
 the semiconductor body moreover includes a semiconductor substrate and the buffer layer moreover includes an electrical-conduction layer of a compound formed by elements of Groups III-V of an intrinsic type or with N-type doping,   forming the resistive region includes forming the latter on the electrical-conduction layer and underneath the heterostructure, and   forming the gate electrode includes extending the gate electrode in the semiconductor body at least to the electrical-conduction layer.   
     
     
         13 . The method according to  claim 8 , wherein:
 the semiconductor body moreover includes: a semiconductor substrate; and an interface layer of a compound formed by elements of Groups III-V that extends between the substrate and the buffer region, and   forming the gate electrode comprises extending the gate electrode in the semiconductor body at least to the interface layer.   
     
     
         14 . A high-electron-mobility transistor, comprising:
 a semiconductor body including a buffer region and a heterostructure extending over the buffer region;   a gate recessed electrode extending in the semiconductor body at least partially through the buffer region; and   a first working electrode and a second working electrode, which extend at respective sides of the gate electrode; wherein:   the buffer region is configured to house, in a first operating condition in which a voltage between the gate electrode and the first working electrode is higher than a threshold voltage, a conductive path for a flow of an electric current between the first and second working electrodes   the buffer region includes a resistive region configured to hinder, in a second operating condition in which the voltage between the gate electrode and the first working electrode is lower than the threshold voltage, the electric current flow between the first and second working electrodes, and   the gate electrode extends in the semiconductor body to a depth, in said direction, equal to, or greater than, a maximum depth reached by the resistive region.   
     
     
         15 . The high-electron-mobility transistor according to  claim 14 , wherein said heterostructure comprises a channel layer, of a material that is a compound formed by elements of Groups III-V including nitride, and an electron-supply layer extending over the channel layer. 
     
     
         16 . The high-electron-mobility transistor according to  claim 14 , wherein the resistive region is an implanted region of the heterostructure and extends between the gate electrode and at least one of the first working electrode and the second working electrode. 
     
     
         17 . The high-electron-mobility transistor according to  claim 16 , wherein the resistive region has a density of dopant species comprised between 10 15  ions/cm 3  and 10 20  ions/cm 3 . 
     
     
         18 . The high-electron-mobility transistor according to  claim 14 , wherein the resistive region is a layer of a compound formed by elements of Groups III-V with a doping of a P-type, extending underneath the heterostructure. 
     
     
         19 . The high-electron-mobility transistor according to  claim 14 , wherein:
 the semiconductor body includes a semiconductor substrate;   the buffer region extends over the substrate and includes an electrical-conduction layer of a compound formed by elements of Groups III-V of an intrinsic type or with N-type doping;   the resistive region extends on the electrical-conduction layer; and   the gate electrode extends in the semiconductor body at least to the electrical-conduction layer.   
     
     
         20 . The high-electron-mobility transistor according to  claim 14 , wherein:
 the semiconductor body includes a semiconductor substrate; and an interface layer of a compound formed by elements of Groups III-V and extending between the substrate and the buffer region, and   the gate electrode extends in the semiconductor body at least to the interface layer.   
     
     
         21 . The high-electron-mobility transistor according to  claim 14 , wherein:
 the heterostructure includes a barrier layer of a first semiconductor material and a channel layer of a second semiconductor material that is different from the first semiconductor material; and   the resistive region is an implanted region positioned in the barrier layer and channel layer of the heterostructure and extends between the gate electrode and at least one of the first working electrode and the second working electrode.   
     
     
         22 . The normally-off electronic device according to  claim 1 , wherein:
 the heterostructure includes a barrier layer of a first semiconductor material and a channel layer of a second semiconductor material that is different from the first semiconductor material; and   the resistive region is an implanted region positioned in the barrier layer and channel layer of the heterostructure and extends between the gate electrode and at least one of the first working electrode and the second working electrode.   
     
     
         23 . The method according to  claim 8 , wherein:
 the heterostructure includes a barrier layer of a first semiconductor material and a channel layer of a second semiconductor material that is different from the first semiconductor material; and   forming the resistive region includes implanting dopant species in the barrier layer and channel layer of the heterostructure and between the gate electrode and at least one of the first working electrode and the second working electrode.