Antifuse-type one time programming memory cell and array structure with same

Abstract

An antifuse-type one time programming memory cell, comprising: a first select transistor, wherein a first drain/source terminal of the first select transistor is connected with a bit line, and a gate terminal of the first select transistor is connected with a word line; an antifuse transistor, wherein a first drain/source terminal of the antifuse transistor is connected with a second drain/source terminal of the first select transistor, and a gate terminal of the antifuse transistor is connected with an antifuse control line; and a second select transistor, wherein a first drain/source terminal of the second select transistor is connected with a second drain/source terminal of the antifuse transistor, a gate terminal of the second select transistor is connected with the word line, and a second drain/source terminal of the second select transistor is connected with the bit line.

What is claimed is: 
     
         1 . An antifuse-type one time programming memory cell, comprising:
 a first select transistor, wherein a first drain/source terminal of the first select transistor is connected with a bit line, and a gate terminal of the first select transistor is connected with a word line;   an antifuse transistor, wherein a first drain/source terminal of the antifuse transistor is connected with a second drain/source terminal of the first select transistor, and a gate terminal of the antifuse transistor is connected with an antifuse control line; and   a second select transistor, wherein a first drain/source terminal of the second select transistor is connected with a second drain/source terminal of the antifuse transistor, a gate terminal of the second select transistor is connected with the word line, and a second drain/source terminal of the second select transistor is connected with the bit line.   
     
     
         2 . An array structure connected with a first bit line, a first word line, a second word line, a first antifuse control line and a second antifuse control line, the array structure comprising:
 a first memory cell comprising:
 a first select transistor, wherein a first drain/source terminal of the first select transistor is connected with the first bit line, and a gate terminal of the first select transistor is connected with the first word line; 
 a first antifuse transistor, wherein a first drain/source terminal of the first antifuse transistor is connected with a second drain/source terminal of the first select transistor, and a gate terminal of the first antifuse transistor is connected with the first antifuse control line; and 
 a second select transistor, wherein a first drain/source terminal of the second select transistor is connected with a second drain/source terminal of the first antifuse transistor, a gate terminal of the second select transistor is connected with the first word line, and a second drain/source terminal of the second select transistor is connected with the first bit line; and 
   a second memory cell comprising:
 a third select transistor, wherein a first drain/source terminal of the third select transistor is connected with the first bit line, and a gate terminal of the third select transistor is connected with the second word line; 
 a second antifuse transistor, wherein a first drain/source terminal of the second antifuse transistor is connected with a second drain/source terminal of the third select transistor, and a gate terminal of the second antifuse transistor is connected with the second antifuse control line; and 
 a fourth select transistor, wherein a first drain/source terminal of the fourth select transistor is connected with a second drain/source terminal of the second antifuse transistor, a gate terminal of the fourth select transistor is connected with the second word line, and a second drain/source terminal of the fourth select transistor is connected with the first bit line. 
   
     
     
         3 . The array structure as claimed in  claim 2 , further comprising:
 a third memory cell comprising:
 a fifth select transistor, wherein a first drain/source terminal of the fifth select transistor is connected with a second bit line, and a gate terminal of the fifth select transistor is connected with the first word line; 
 a third antifuse transistor, wherein a first drain/source terminal of the third antifuse transistor is connected with a second drain/source terminal of the fifth select transistor, and a gate terminal of the third antifuse transistor is connected with the first antifuse control line; and 
 a sixth select transistor, wherein a first drain/source terminal of the sixth select transistor is connected with a second drain/source terminal of the third antifuse transistor, a gate terminal of the sixth select transistor is connected with the first word line, and a second drain/source terminal of the sixth select transistor is connected with the second bit line; and 
   a fourth memory cell comprising:
 a seventh select transistor, wherein a first drain/source terminal of the seventh select transistor is connected with the second bit line, and a gate terminal of the seventh select transistor is connected with the second word line; 
 a fourth antifuse transistor, wherein a first drain/source terminal of the fourth antifuse transistor is connected with a second drain/source terminal of the seventh select transistor, and a gate terminal of the fourth antifuse transistor is connected with the second antifuse control line; and 
 an eighth select transistor, wherein a first drain/source terminal of the eighth select transistor is connected with a second drain/source terminal of the fourth antifuse transistor, a gate terminal of the eighth select transistor is connected with the second word line, and a second drain/source terminal of the eighth select transistor is connected with the second bit line.