System and method for updating an instruction cache following a branch instruction in a semiconductor device

Abstract

A semiconductor device includes a memory for storing a plurality of instructions therein, an instruction queue which temporarily stores the instructions fetched from the memory therein, a central processing unit which executes the instruction supplied from the instruction queue, an instruction cache which stores therein the instructions executed in the past by the central processing unit, and a control circuit which controls fetching of each instruction. When the central processing unit executes a branch instruction, and an instruction of a branch destination is being in the instruction cache and an instruction following the instruction of the branch destination is stored in the instruction queue, the control circuit causes the instruction queue to fetch the instruction of the branch destination from the instruction cache and causes the instruction queue not to fetch the instruction following the instruction of the branch destination.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a central processing unit (CPU);   a memory that stores a plurality of instructions;   an instruction cache that stores instructions executed by the CPU; and   an instruction queue that stores instructions fetched from one of the memory and the instruction cache, and provides the CPU with the stored instructions,   wherein the instruction queue has a first area that stores a branch instruction and a second area that stores an instruction following a branch destination instruction of the branch instruction,   wherein when the CPU executes the branch instruction and the branch destination instruction is stored in the instruction cache, the instruction cache provides the first area with the branch destination instruction.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein when the branch destination instruction is not stored in the instruction cache, the instruction queue is reset. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein when the second area does not store the instruction following the branch destination instruction of the branch instruction, the instruction queue is reset. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein when the instruction cache provides the first area with the branch destination instruction, a fetch of an additional instruction is inhibited. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein:
 when the branch destination instruction is not stored in the instruction cache, the instruction queue is reset;   when the second area does not store the instruction following the branch destination instruction of the branch instruction, the instruction queue is reset; and   when the instruction cache provides the first area with the branch destination instruction, a fetch of an additional instruction is inhibited.   
     
     
         6 . The semiconductor device according to  claim 1 , wherein:
 when the branch destination instruction is not stored in the instruction cache, the instruction queue is reset; and   when the second area does not store the instruction following the branch destination instruction of the branch instruction, the instruction queue is reset.   
     
     
         7 . The semiconductor device according to  claim 1 , wherein:
 when the branch destination instruction is not stored in the instruction cache, the instruction queue is reset; and   when the instruction cache provides the first area with the branch destination instruction, a fetch of an additional instruction is inhibited.   
     
     
         8 . The semiconductor device according to  claim 1 , wherein:
 when the second area does not store the instruction following the branch destination instruction of the branch instruction, the instruction queue is reset; and   when the instruction cache provides the first area with the branch destination instruction, a fetch of an additional instruction is inhibited.