Memory buffers and modules supporting dynamic point-to-point connections

Abstract

A memory module comprises a module interface having module data-group ports to communicate data as respective data groups, a command port to receive memory-access commands, a first memory device including a first device data-group port, a second memory device including a second device data-group port, and a signal buffer coupled between the module interface and each of the first and second devices. In a first mode, in response to the memory-access commands, the signal buffer communicates the data group associated with each of the first and second device data-group ports via a respective one of the module data-group ports. In a second mode, in response to the memory-access commands, the signal buffer alternatively communicates the data group associated with the first device data-group port or the data group associated with the second device data-group port via the same one of the module data-group ports.

1 . (canceled) 
     
     
         2 . A width-configurable memory module comprising:
 module data-group ports to communicate first data and second data;   a first rank group of first memory devices to store the first data;   a second rank group of second memory devices to store the second data;   a register to store at least one of a first value indicative of a first module width and a second value indicative of a second module width;   a command router coupled to the register, the first memory devices, and the second memory devices, the router:
 to communicate the first data from the first memory devices and the second data from the second memory devices over a first subset of the module data-group ports responsive to the first value indicative of the first module width; and 
 to communicate the first data from the first memory devices over the first subset of the module data-group ports and the second data from the second memory over a second subset of the module data-group ports responsive to the second value indicative of the second module width. 
   
     
     
         3 . The memory module of  claim 2 , the command router coupled to the first memory devices via a first command bus and the second memory devices via a second command bus. 
     
     
         4 . The memory module of  claim 2 , further comprising a module command port coupled to the command router to receive module commands, wherein the command router selects between the first memory devices and the second memory devices responsive to an address bit of the module command port. 
     
     
         5 . The memory module of  claim 2 , further comprising a module command port coupled to the command router to receive module commands, wherein the command router selects between the first memory devices and the second memory devices responsive to a chip-select bit of the module command port. 
     
     
         6 . The memory module of  claim 2 , wherein the first memory devices are coupled to the command router via respective first device data-group ports, the second memory devices are coupled to the command router via respective second device data-group ports, and wherein the number of the module data-group ports equals a sum of the numbers of the first data-group port and the second device data-group ports. 
     
     
         7 . The memory module of  claim 2 , wherein the first memory devices and the second memory devices are equal in number. 
     
     
         8 . The memory module of  claim 2 , wherein the first module width is half the second module width. 
     
     
         9 . The memory module of  claim 2 , wherein each of the first memory devices communicates a respective subset of the first data via only one of the module data-group ports. 
     
     
         10 . The memory module of  claim 2 , wherein the first memory devices and the second memory devices communicate the first data and the second data with the module data-group ports via the command router. 
     
     
         11 . The memory module of  claim 10 , wherein the command router is coupled to each of the first memory devices and each of the second memory devices via a respective data bus. 
     
     
         12 . A memory system comprising:
 a memory controller; and   at least one width-configurable memory module, each memory module comprising:
 module data-group ports to communicate first data and second data; 
 a first rank group of first memory devices to store the first data; 
 a second rank group of second memory devices to store the second data; 
 a register to store at least one of a first value indicative of a first module width and a second value indicative of a second module width; 
 a command router coupled to the register, the first memory devices, and the second memory devices, the router:
 to direct communication of the first data from the first memory devices and the second data from the second memory devices over a first subset of the module data-group ports responsive to the first value indicative of the first module width; and 
 to direct communication of the first data from the first memory devices over the first subset of the module data-group ports and the second data from the second memory over a second subset of the module data-group ports responsive to the second value indicative of the second module width. 
 
   
     
     
         13 . The memory system of  claim 12 , the command router of each of the memory modules coupled to the first memory devices via a first command bus and the second memory devices via a second command bus. 
     
     
         14 . The memory system of  claim 12 , further comprising a module command port coupled between the memory controller and the command router on each of the memory modules. 
     
     
         15 . The memory system of  claim 14 , the memory controller to detect a number of modules in the at least one memory module and load the register in each of the number of modules with one of the first value or the second value responsive to detected number. 
     
     
         16 . The memory system of  claim 15 , wherein the first module width is half the second module width. 
     
     
         17 . The memory system of  claim 12 , the register to store at least one of the first value, the second value, and a third value indicative of a third module width. 
     
     
         18 . The memory system of  claim 12 , wherein the command router buffers commands from the memory controller to the command router. 
     
     
         19 . The memory system of  claim 18 , wherein the command router buffers the first data from the first memory devices to the memory controller and buffers the second data from the second memory devices to the memory controller. 
     
     
         20 . The memory system of  claim 19 , wherein the command router buffers write data from the memory controller to the first memory devices and the second memory devices. 
     
     
         21 . The memory system of  claim 12 , wherein the memory devices are DRAM devices.