Systems and methods for providing local hardware limit management and enforcement

Abstract

Systems and methods for providing local hardware limit management and enforcement are described. One embodiment includes a system for managing and enforcing hardware limits on a system on chip (SoC). The system includes a plurality of chip components provided on a system on chip (SoC). A network of local limit manager (LLM) components is distributed on the SoC. Each LLM component is in communication with a corresponding sensor module that monitors one or more of the chip components. Each LLM component comprises a generic hardware structure for enforcing one or more hardware limits associated with the corresponding sensor module.

1 . A system for managing hardware limits on a system on chip (SoC), the system comprising:
 a plurality of chip components provided on a system on chip (SoC);   a network of local limit manager (LLM) components distributed on the SoC, each LLM component in communication with a corresponding sensor module that monitors one or more of the chip components, each LLM component comprising a generic hardware structure for enforcing one or more hardware limits associated with the corresponding sensor module.   
     
     
         2 . The system of  claim 1 , wherein the chip components comprise one or more of a central processing unit (CPU), a graphics processing unit (GPU), and a digital signal processor (DSP). 
     
     
         3 . The system of  claim 1 , wherein one or more of the sensor modules comprise a digital power meter (DPM) configured to store estimated current consumption of the monitored chip component in a sensor data register embodied in the corresponding LLM component. 
     
     
         4 . The system of  claim 3 , wherein the LLM component embodying the sensor data register is configured to:
 compare the estimated current consumption stored in the sensor data register against a local hardware limit stored in a limits threshold register; and   if the local hardware limit is exceeded, initiate one or more throttling actions defined in a throttling action register.   
     
     
         5 . The system of  claim 1 , wherein the one or more hardware limits comprise one or more of a power delivery network (PDN) transient limit, a current limit, a thermal limit, a battery current limit, and a voltage rail current limit associated with power management integrated circuit (PMIC) or a switched mode power supply (SMPS). 
     
     
         6 . The system of  claim 1 , wherein the generic hardware structure of each LLM comprises:
 a sensor data register for storing the sensor data from the associated sensor module;   a threshold register for storing one or more coefficients for determining whether the sensor data exceeds the one or more hardware limits; and   a throttling actions register for storing one or more predefined throttling actions to be initiated if the sensor data exceeds the one or more hardware limits.   
     
     
         7 . The system of  claim 1 , wherein the LLM components are configured to sample the sensor data at a programmable time constant. 
     
     
         8 . The system of  claim 1 , further comprising one or more domain limit manager (DLM) components residing on the SoC, each DLM component in communication with a portion of the plurality of LLM components in a parent/child relationship, wherein the parent DLM component is configured to budget the one or more hardware limits to the plurality of associated child LLM components. 
     
     
         9 . The system of  claim 8 , wherein each DLM component comprises a separate voltage domain associated with a corresponding switched mode power supply (SMPS). 
     
     
         10 . The system of  claim 8 , wherein one or more of the DLM components is configured to budget a battery current consumption to the associated child LLM components. 
     
     
         11 . A method for providing hardware limit management and enforcement, the method comprising:
 a sensor module monitoring a chip component on a system on chip (SoC);   storing sensor data from the sensor module in a local limit management (LLM) hardware component;   storing a hardware limit associated with the sensor module in the LLM hardware component;   comparing the sensor data to the hardware limit; and   if the sensor data exceeds the hardware limit, initiating a predefined throttling action for enforcing the hardware limit, wherein the hardware limit comprises one or more of a power delivery network (PDN) transient limit, a current limit, a thermal limit, a battery current limit, and a voltage rail current limit associated with power management integrated circuit (PMIC) or a switched mode power supply (SMPS).   
     
     
         12 . The method of  claim 11 , wherein the chip component comprises one or more of a central processing unit (CPU), a graphics processing unit (GPU), and a digital signal processor (DSP). 
     
     
         13 . The method of  claim 11 , wherein the sensor module comprises a digital power meter (DPM) and the sensor data comprises estimated current consumption of the monitored chip component. 
     
     
         14 . (canceled) 
     
     
         15 . The method of  claim 11 , wherein the hardware limit is programmable. 
     
     
         16 . The method of  claim 11 , wherein the storing the sensor data in the LLM hardware component further comprises sampling the sensor data at a predefined time constant. 
     
     
         17 . The method of  claim 11 , further comprising: associating the LLM hardware component with a domain limit manager (DLM) component in a parent/child relationship, wherein the parent DLM component is configured to budget the hardware limit to the child LLM components. 
     
     
         18 . The method of  claim 17 , wherein the sensor data comprises an estimated current consumption of the monitored chip component, and the parent DLM component budgets a battery current consumption to the child LLM components. 
     
     
         19 . A system for providing hardware limit management and enforcement, the system comprising:
 means for monitoring a chip component on a system on chip (SoC);   means for storing sensor data from the sensor module in a local limit management (LLM) hardware component;   means for storing a hardware limit associated with the sensor module in the LLM hardware component;   means for comparing the sensor data to the hardware limit; and   means for initiating a predefined throttling action for enforcing the hardware limit if the sensor data exceeds the hardware limit.   
     
     
         20 . The system of  claim 19 , wherein the chip component comprises one or more of a central processing unit (CPU), a graphics processing unit (GPU), and a digital signal processor (DSP). 
     
     
         21 . The system of  claim 19 , wherein the means for monitoring the chip component comprises a digital power meter (DPM) and the sensor data comprises estimated current consumption of the monitored chip component. 
     
     
         22 . The system of  claim 19 , wherein the hardware limit comprises one or more of a power delivery network (PDN) transient limit, a current limit, a thermal limit, a battery current limit, and a voltage rail current limit associated with power management integrated circuit (PMIC) or a switched mode power supply (SMPS). 
     
     
         23 . The system of  claim 19 , wherein the hardware limit is programmable. 
     
     
         24 . The system of  claim 19 , wherein the means for storing the sensor data in the LLM hardware component further comprises means for sampling the sensor data at a predefined time constant. 
     
     
         25 . The system of  claim 19 , further comprising: means for associating the LLM hardware component with a domain limit manager (DLM) component in a parent/child relationship, wherein the parent DLM component is configured to budget the hardware limit to the child LLM components. 
     
     
         26 . The system of  claim 25 , wherein the sensor data comprises an estimated current consumption of the monitored chip component, and the parent DLM component budgets a battery current consumption to the child LLM components. 
     
     
         27 . A system for managing and enforcing hardware limits on a system on chip (SoC), the system comprising:
 a system on chip comprising a plurality of chip components; and   an interconnected network of local limit manager (LLM) components dispersed over an area of the SoC, each LLM component in communication with a corresponding sensor module that monitors one or more of the chip components, each LLM component comprising a generic hardware structure for enforcing one or more hardware limits associated with the corresponding sensor module;   wherein the generic hardware structure of each LLM comprises:
 a sensor data register for storing the sensor data from the associated sensor module; 
 a threshold register for storing one or more coefficients for determining whether the sensor data exceeds the one or more hardware limits; and 
 a throttling actions register for storing one or more predefined throttling actions to be initiated if the sensor data exceeds the one or more hardware limits. 
   
     
     
         28 . The system of  claim 27 , wherein an estimated current consumption of the monitored chip component is stored in the sensor data register, and the LLM component embodying the sensor data register is configured to:
 compare the estimated current consumption stored in the sensor data register against a local hardware limit stored in a limits threshold register; and   if the local hardware limit is exceeded, initiate one or more throttling actions defined in the throttling action register.   
     
     
         29 . The system of  claim 27 , wherein the one or more hardware limits comprise one or more of a power delivery network (PDN) transient limit, a current limit, a thermal limit, a battery current limit, and a voltage rail current limit associated with power management integrated circuit (PMIC) or a switched mode power supply (SMPS). 
     
     
         30 . The system of  claim 27 , further comprising one or more domain limit manager (DLM) components residing on the SoC, each DLM component in communication with a portion of the plurality of LLM components in a parent/child relationship, wherein the parent DLM component is configured to budget the one or more hardware limits to the plurality of associated child LLM components.