Semiconductor memory device and method of controlling the same

Abstract

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

1 . (canceled) 
     
     
         2 . A processor for controlling a memory comprising:
 an interface;   a first circuit coupled to the interface;   a second circuit for interfacing with the memory; and   a third circuit coupled to the second circuit,   wherein the first circuit is configured to:   generate error detection data for data received from the interface; and   check data transmitted to the interface, and   wherein the third circuit is configured to:   generate error correction data for data and first error correction data transmitted to the second circuit; and   check data and first error correction data received from the second circuit.   
     
     
         3 . The processor of  claim 2 , wherein the first circuit is configured to generate error detection data per received unit of data. 
     
     
         4 . The processor of  claim 3 , wherein
 the data received from the interface comprises a data payload including a number of units of data, and   the data received from the interface comprises streaming data.   
     
     
         5 . The processor of  claim 2 , wherein
 the first circuit comprises a cyclic redundancy check (CRC) engine coupled to the interface, and   the third circuit comprises an error correction code (ECC) engine.   
     
     
         6 . The processor of  claim 2 , wherein the processor includes:
 a fourth circuit coupled to the interface and to the second and third circuits; and   an error detection memory coupled to the fourth circuit,   wherein the error detection memory is configured to store the error detection data.   
     
     
         7 . The processor of  claim 6 , wherein the processor includes a data buffer coupled to the fourth circuit and to the third circuit, and
 wherein the data buffer is configured to buffer data for the third circuit.   
     
     
         8 . The processor of  claim 2 , wherein the third circuit is configured to correct one or more errors in the data received from the second circuit. 
     
     
         9 . The processor of  claim 2 , wherein the processor is configured to transfer the data received from the interface, the error detection data, and the error correction data across the second circuit. 
     
     
         10 . The processor of  claim 2 , wherein the processor includes a fourth circuit coupled to the second circuit and to the first and third circuits, and
 wherein the fourth circuit is configured to receive data and corresponding error detection data from the second circuit and to transfer the data and the corresponding error detection data to the first circuit.   
     
     
         11 . The processor of  claim 10 , wherein the first circuit is configured to:
 generate error detection data for the data received from the fourth circuit; and   compare the generated error detection data for the data received from the fourth circuit to the corresponding error detection data received from the fourth circuit.   
     
     
         12 . The processor of  claim 10 , wherein the processor includes:
 more than one channel;   a channel data transfer circuit coupled to the fourth circuit;   a data buffer coupled to the channel data transfer circuit and the third circuit; and   an error detection circuit coupled to the second circuit.   
     
     
         13 . A method for operating a processor, comprising:
 generating, with a first circuit, error detection data for data received from an interface coupled to the first circuit;   checking, with the first circuit, data transmitted to the interface;   generating, with a third circuit, error correction data for data and first error correction data transmitted to a second circuit coupled to the third circuit; and   checking, with the third circuit, data and first error correction data received from the second circuit.   
     
     
         14 . The method of  claim 13 , wherein generating the error detection data for the data received from the interface comprises generating error detection data per unit of data received from the interface. 
     
     
         15 . The method of  claim 14 , wherein
 the data received from the interface comprises a data payload including a number of units of data; and   the data received from the interface comprises streaming data.   
     
     
         16 . The method of  claim 13 , wherein
 the first circuit comprises a cyclic redundancy check (CRC) engine coupled to the interface, and   the third circuit comprises an error correction code (ECC) engine.   
     
     
         17 . The method of  claim 13 , wherein the method includes storing the error detection data in an error detection memory coupled to a fourth circuit, which is coupled to the interface and to the second and third circuits. 
     
     
         18 . The method of  claim 17 , wherein the method includes buffering data for the third circuit with a data buffer coupled to the fourth circuit and to the third circuit. 
     
     
         19 . The method of  claim 13 , wherein the method includes correcting, with the third circuit, one or more errors in the data received from the second circuit. 
     
     
         20 . The method of  claim 13 , wherein the method includes transferring the data received from the interface, the error detection data, and the error correction data across the second circuit. 
     
     
         21 . The method of  claim 13 , wherein the method includes:
 receiving, with a fourth circuit coupled to the second circuit and to the first and third circuits, data and corresponding error detection data from the second circuit; and   transferring, with the fourth circuit, the data and the corresponding error detection data to the first circuit.   
     
     
         22 . The method of  claim 21 , wherein generating with the first circuit includes generating error detection data for the data received from the fourth circuit, and
 wherein the method includes comparing, with the first circuit, the generated error detection data for the data received from the fourth circuit to the corresponding error detection data received from the fourth circuit.   
     
     
         23 . The method of  claim 21 , wherein receiving includes receiving with the fourth circuit including more than one channel. 
     
     
         24 . A processor for controlling a memory comprising:
 an interface;   a first circuit coupled to the interface;   a second circuit for interfacing with the memory; and   a third circuit coupled to the second circuit,   wherein the first circuit is configured to:   generate first error detection data for data received from the interface; and   check data transmitted to the interface, and   wherein the third circuit is configured to check data and error correction data received from the second circuit.   
     
     
         25 . The processor of  claim 24 , wherein the first circuit is configured to generate error detection data per received unit of data. 
     
     
         26 . The processor of  claim 25 , wherein
 the data received from the interface comprises a data payload including a number of units of data, and   the data received from the interface comprises streaming data.   
     
     
         27 . The processor of  claim 24 , wherein
 the first circuit comprises a cyclic redundancy check (CRC) engine coupled to the interface, and   the third circuit comprises an error correction code (ECC) engine.   
     
     
         28 . The processor of  claim 24 , wherein the processor includes:
 a fourth circuit coupled to the interface and to the second and third circuits; and   an error detection memory coupled to the fourth circuit,   wherein the error detection memory is configured to store the error detection data.   
     
     
         29 . The processor of  claim 28 , wherein the processor includes a data buffer coupled to the fourth circuit and to the third circuit, and
 wherein the data buffer is configured to buffer data for the third circuit.   
     
     
         30 . The processor of  claim 24 , wherein the third circuit is configured to correct one or more errors in the data received from the second circuit. 
     
     
         31 . The processor of  claim 24 , wherein the processor is configured to transfer the data received from the interface, the error detection data, and the error correction data across the second circuit. 
     
     
         32 . The processor of  claim 24 , wherein the processor includes a fourth circuit coupled to the second circuit and to the first and third circuits, and
 wherein the fourth circuit is configured to receive data and corresponding error detection data from the second circuit and to transfer the data and the corresponding error detection data to the first circuit.   
     
     
         33 . The processor of  claim 32 , wherein the first circuit is configured to:
 generate error detection data for the data received from the fourth circuit; and   compare the generated error detection data for the data received from the fourth circuit to the corresponding error detection data received from the fourth circuit.   
     
     
         34 . The processor of  claim 32 , wherein the processor includes:
 more than one channel;   a channel data transfer circuit coupled to the fourth circuit;   a data buffer coupled to the channel data transfer circuit and the third circuit; and   an error detection circuit coupled to the second circuit.   
     
     
         35 . A memory system comprising:
 a memory; and   a processor for control the memory,   wherein the processor comprises:   an interface;   a first circuit coupled to the interface;   a second circuit for interfacing with the memory; and   a third circuit coupled to the second circuit,   wherein the first circuit is configured to:   generate first error detection data for data received from the interface; and   check data transmitted to the interface, and   wherein the third circuit is configured to:   generate error correction data for data and first error correction data transmitted to the second circuit; and   check data and error correction data received from the second circuit.   
     
     
         36 . The memory system of  claim 35 , wherein the first circuit is configured to generate error detection data per received unit of data. 
     
     
         37 . The memory system of  claim 36 , wherein
 the data received from the interface comprises a data payload including a number of units of data; and   the data received from the interface comprises streaming data.   
     
     
         38 . The memory system of  claim 35 , wherein
 the first circuit comprises a cyclic redundancy check (CRC) engine coupled to the interface, and   the third circuit comprises an error correction code (ECC) engine.   
     
     
         39 . The memory system of  claim 35 , wherein the processor includes:
 a fourth circuit coupled to the interface and to the second and third circuits; and   an error detection memory coupled to the fourth circuit,   wherein the error detection memory is configured to store the error detection data.   
     
     
         40 . The memory system of  claim 39 , wherein the processor includes a data buffer coupled to the fourth circuit and to the third circuit, and
 wherein the data buffer is configured to buffer data for the third circuit.   
     
     
         41 . The memory system of  claim 35 , wherein the third circuit is configured to correct one or more errors in the data received from the second circuit. 
     
     
         42 . The memory system of  claim 35 , wherein the processor is configured to transfer the data received from the interface, the error detection data, and the error correction data across the second circuit. 
     
     
         43 . The memory system of  claim 35 , wherein the processor includes a fourth circuit coupled to the second circuit and to the first and third circuits, and
 wherein the fourth circuit is configured to receive data and corresponding error detection data from the second circuit and to transfer the data and the corresponding error detection data to the first circuit.   
     
     
         44 . The memory system of  claim 43 , wherein the first circuit is configured to:
 generate error detection data for the data received from the fourth circuit; and   compare the generated error detection data for the data received from the fourth circuit to the corresponding error detection data received from the fourth circuit.   
     
     
         45 . The memory system of  claim 43 , wherein the processor includes:
 more than one channel;   a channel data transfer circuit coupled to the fourth circuit;   a data buffer coupled to the channel data transfer circuit and the third circuit; and   an error detection circuit coupled to the second circuit.   
     
     
         46 . The memory system of  claim 35 , wherein the processor includes a fifth circuit comprising an error correction code (ECC) engine. 
     
     
         47 . The memory system of  claim 35 , wherein the data is written into the memory by page unit. 
     
     
         48 . The memory system of  claim 47 , wherein
 the data is erased from the memory by block unit, and   the block unit comprises pages.   
     
     
         49 . The memory system of  claim 35 , wherein the memory includes:
 memory cell transistors; and   word lines, and   the processor is configured to write and read for each set of a plurality of memory cell transistors.   
     
     
         50 . The memory system of  claim 35 , wherein the processor is configured to write data as a size of 512 bytes. 
     
     
         51 . The memory system of  claim 35 , wherein a BHC code, Reed-Solomon (RS) code, or LDPC (Low Density Parity Check) code is usable as the error correction data. 
     
     
         52 . The memory system of  claim 35 , wherein each of the data and the first error correction data transmitted to the second circuit has a size corresponding to write data of 4096 bits and error-detecting code of 32 bits. 
     
     
         53 . The memory system of  claim 35 , wherein each of the data and error correction data received from the second circuit has a size corresponding to write data (4096 bits)×8+error-detecting code (32 bits)×8. 
     
     
         54 . The memory system of  claim 35 , wherein each of the data and error correction data received from the second circuit corrects a 12-bit error in a data block. 
     
     
         55 . The memory system of  claim 35 , wherein the error correction data generated by the third circuit has a size of 192 bits.