Butted Body Contact for SOI Transistor

Abstract

Systems, methods, and apparatus for an improved body tie construction that produces all the benefits of conventional body tie (H-gate, T-gate), without the limitations and degradations associated with those constructions are described. The improved body tie construction is configured to have a lower resistance body tie when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie.

1 . A field-effect transistor (FET) comprising:
 a drain region having a first conductivity type;   a source region having the first conductivity type;   a gate polysilicon structure defining a body region, the body region having a second conductivity type;   at least one body contact region of the second conductivity type in contact with the source region and separate from the body region;   and at least one body tab of the second conductivity type in contact with the body region and the at least one body contact region, configured to electrically connect the at least one body contact region to the body region.   
     
     
         2 . The field-effect transistor (FET) according to  claim 1 , wherein the FET is a silicon-on-insulator (SOI) FET, fabricated using a silicon-on-insulator (SOI) technology. 
     
     
         3 . The field effect transistor (FET) according to  claim 2 , wherein a silicon layer of the SOI FET is a thin-film silicon layer. 
     
     
         4 . The field-effect transistor (FET) according to  claim 3 , wherein the at least one body contact region is fully contained within the source region. 
     
     
         5 . The field-effect transistor (FET) according to  claim 3 , wherein the at least one body contact region abuts the source region. 
     
     
         6 . The field-effect transistor (FET) according to  claim 3 , wherein the at least one body tab comprises two or more body tabs. 
     
     
         7 . The field-effect transistor (FET) according to  claim 6 , wherein the two or more body tabs are symmetrically placed along a width of the body region. 
     
     
         8 . The field-effect transistor (FET) according to  claim 3 , wherein the at least one body contact region comprises two or more body contact regions. 
     
     
         9 . The field-effect transistor (FET) according to  claim 3 , further comprising at least one polysilicon tab configured to define the at least one body tab. 
     
     
         10 . The field-effect transistor (FET) according to  claim 9 , wherein the at least one polysilicon tab and the gate polysilicon structure form a single polysilicon structure. 
     
     
         11 . The field-effect transistor (FET) according to  claim 9  or  claim 10 , wherein the at least one body tab provides a resistive conduction path between the body region and the body contact region with a resistance value which is a function of the ON or OFF state of the FET. 
     
     
         12 . The field-effect transistor (FET) according to  claim 11 , wherein the resistance value can be adjusted via a length and a width of the at least one body tab. 
     
     
         13 . The field-effect transistor (FET) according to  claim 11 , wherein the resistance value in the ON (conduction) state of the FET is substantially higher than the resistance value in the OFF (non-conduction) state of the FET. 
     
     
         14 . The field-effect transistor (FET) according to  claim 11 , wherein the resistance value in the ON (conduction) state of the FET is at least ten times the resistance value in the OFF (non-conduction) state of the FET. 
     
     
         15 . The field-effect transistor (FET) according to  claim 3 , further comprising a conductive layer atop the source region and the at least one body contact region. 
     
     
         16 . The field-effect transistor (FET) according to  claim 15 , wherein the conductive layer is a silicide layer. 
     
     
         17 . The field-effect transistor (FET) according to  claim 3 , further comprising a conductive contact atop a portion of the at least one body contact region. 
     
     
         18 . The field-effect transistor (FET) according to  claim 3 , wherein the transistor is a metal-oxide-semiconductor field effect transistor (MOSFET). 
     
     
         19 . The field-effect transistor (FET) according to  claim 18 , wherein the MOSFET is an N-type MOSFET with the drain region and the source region being N+ type regions, the body region and the at least one body tab being P− type regions, and the at least one body contact being a P+ type region. 
     
     
         20 . The field-effect transistor (FET) according to  claim 18 , wherein the MOSFET is an P-type MOSFET with the drain region and the source region being P+ type regions, the body region and the at least one body tab being N− type regions, and the at least one body contact being a N+ type region. 
     
     
         21 . The field-effect transistor (FET) according to  claim 2 , further comprising:
 an insulating layer; and   a silicon layer overlying the insulating layer,   wherein the drain region, the source region, the body region, the at least one body contact region, and the body tab are formed in the silicon layer and extend through the silicon layer to reach the insulating layer.   
     
     
         22 . A multi-finger field-effect transistor (FET) comprising:
 a first gate polysilicon structure defining a first body region, the first body region having a first conductivity type;   a second gate polysilicon structure defining a second body region, the second body region having the first conductivity type;   a first drain region adjacent to the first body region having a second conductivity type;   a second drain region adjacent to the second body region having the second conductivity type;   a common source region adjacent to the first and the second body regions having the second conductivity type;   at least one body contact region of the first conductivity type formed within the common source region and separate from the first and the second body regions;   at least one first body tab of the first conductivity type in contact with the first body region and the at least one body contact region, configured to electrically connect the at least one body contact region to the first body region, and   at least one second body tab of the first conductivity type in contact with the second body region and the at least one body contact region, configured to electrically connect the at least one body contact region to the second body region.   
     
     
         23 . The multi-finger field-effect transistor (FET) according to  claim 22 , wherein the FET is a silicon-on-insulator (SOI) FET, fabricated using a silicon-on-insulator (SOI) technology. 
     
     
         24 . The field effect transistor (FET) according to  claim 23 , wherein a silicon layer of the SOI FET is a thin-film silicon layer. 
     
     
         25 . The multi-finger field-effect transistor (FET) according to  claim 24 , wherein:
 the at least one body contact region comprises a first body contact region and a second body contact region separate from the first body contact region;   the at least one first body tab is in contact with the first body region and the first body contact region, and   the at least one second body tab is in contact with the second body region and the second body contact region.   
     
     
         26 . The multi-finger field-effect transistor (FET) according to  claim 24 , further comprising at least one first polysilicon tab configured to define the at least one first body tab, and at least one second polysilicon tab configured to define the at least one second body tab. 
     
     
         27 . The multi-finger field-effect transistor (FET) according to  claim 26 , wherein the at least one first polysilicon tab and the at least one second polysilicon tab are joint and form with the first gate polysilicon structure and the second gate polysilicon structure a single polysilicon structure. 
     
     
         28 . The multi-finger field-effect transistor (FET) according to  claim 24 , further comprising an isolation region having the first conductivity type which isolates the at least one body contact region from the common source region. 
     
     
         29 . The multi-finger field-effect transistor (FET) according to  claim 28 , further comprising:
 at least one first polysilicon tab configured to define the at least one first body tab;   at least one second polysilicon tab configured to define the at least one second body tab; and   at least one isolation polysilicon structure configured to define the isolation region.   
     
     
         30 . The multi-finger field-effect transistor (FET) according to  claim 29 , wherein the at least one first polysilicon tab, the at least one second polysilicon tab and the at least one isolation polysilicon structure are joint and form with the first gate polysilicon structure and the second gate polysilicon structure a single polysilicon structure. 
     
     
         31 . The multi-finger field-effect transistor (FET) according to  claim 23 , further comprising:
 an insulating layer; and   a silicon layer overlying the insulating layer,   wherein the first and second drain regions, the first and second body regions, the common source region, the at least one body contact region, and the at least one first body tab are formed in the silicon layer and extend through the silicon layer to reach the insulating layer.   
     
     
         32 . A circuital arrangement comprising:
 a first gate polysilicon structure defining a first body region, the first body region having a first conductivity type;   a second gate polysilicon structure defining a second body region, the second body region having the first conductivity type;   a first drain region associated to the first body region having a second conductivity type;   a first source region associated to the first body region having the second conductivity type;   a second source region associated to the second body region having the second conductivity type;   a second drain region associated to the second body region having the second conductivity type,   the first source region and the second drain region defining a common source/drain region having the second conductivity type;   at least one first body contact region of the first conductivity type in contact with the second source region and separate from the first and the second body regions;   at least one first body tab of the first conductivity type in contact with the second body region and the at least one first body contact region configured to electrically connect the at least one first body contact region to the second body region.   
     
     
         33 . The circuital arrangement according to  claim 32 , wherein:
 the first gate polysilicon structure, the first body region, the first drain region, and the first source region, define a first field-effect transistor (FET),   the second gate polysilicon structure, the second body region, the second drain region, and the second source region, define a second field-effect transistor (FET), and   the first FET and the second FET are each a silicon-on-insulator (SOI) FET, fabricated using a silicon-on-insulator (SOI) technology.   
     
     
         34 . The circuital arrangement according to  claim 33 , wherein a silicon layer of the SOI first FET and SOI second FET is a thin-film silicon layer. 
     
     
         35 . The circuital arrangement according to  claim 34 , wherein the at least one first body contact region abuts the second source region. 
     
     
         36 . The circuital arrangement according to  claim 34 , further comprising:
 at least one second body contact region of the first conductivity type formed within the common source/drain region and separate from the first and the second body regions; and   at least one second body tab of the first conductivity type in contact with the first body region and the at least one second body contact region, configured to electrically connect the at least one second body contact region to the second body region.   
     
     
         37 . The circuital arrangement according to  claim 36 , further comprising at least one first polysilicon tab configured to define the at least one first body tab, and at least one second polysilicon tab configured to define the at least one second body tab. 
     
     
         38 . The circuital arrangement according to  claim 33 , further comprising:
 an insulating layer; and   a silicon layer overlying the insulating layer,   wherein the first and second drain regions, the first and second body regions, the first and second source regions, the at least one body contact region, and the at least one first body tab are formed in the silicon layer and extend through the silicon layer to reach the insulating layer.   
     
     
         39 . A transistor device comprising:
 an electrically insulating layer;   a first region having a first conductivity type;   a second region having the first conductivity type;   a conduction channel between the first region and the second region, the conduction channel having a second conductivity type;   at least one body contact region of the second conductivity type separate from the conduction channel;   and at least one body tab of the second conductivity type in contact with the conduction channel and the at least one body contact region configured to resistively connect the at least one body contact region to the conduction channel with a resistance value dependent on a mode of operation of the transistor device,   wherein:   the first region, the second region, the conduction channel, the at least one body contact region and the at least one body tab are formed atop the electrically insulating layer, thereby making contact with the insulating layer.   
     
     
         40 . The transistor device according to  claim 39 , wherein the transistor device is a silicon-on-insulator (SOI) transistor device, fabricated using a silicon-on-insulator (SOI) technology. 
     
     
         41 . The transistor device according to  claim 40 , wherein a silicon layer of the SOI transistor device is a thin-film silicon layer. 
     
     
         42 . The transistor device according to  claim 41 , wherein the at least one body contact region is fully or partially contained within the first region. 
     
     
         43 . The transistor device according to  claim 42 , further comprising an isolation region formed atop the insulating layer and having the second conductivity type, the isolation region isolating the at least one body contact region from the first region. 
     
     
         44 . The transistor device according to  claim 41 , wherein the at least one body contact region is in contact with the first region. 
     
     
         45 . The transistor device according to  claim 41 , further comprising:
 a first structure formed atop the conduction channel and defining a length and a width of the conduction channel; and   a second structure formed atop the at least one body tab and defining a length and a width of the at least one body tab.   
     
     
         46 . The transistor device according to  claim 45 , wherein the first structure and the second structure form a single integral structure. 
     
     
         47 . The transistor device according to  claim 45 , wherein the resistance value can be adjusted via the length and the width of the at least one body tab. 
     
     
         48 . A field-effect transistor (FET) comprising:
 a drain region having a first conductivity type;   a source region having the first conductivity type;   a gate polysilicon structure defining a body region, the body region having a second conductivity type;   at least one body contact region of the second conductivity type separate from the body region;   and at least one body tab of the second conductivity type in contact with the body region and the at least one body contact region, configured to electrically connect the at least one body contact region to the body region.   
     
     
         49 . The field-effect transistor (FET) according to  claim 48 , further comprising at least one polysilicon tab configured to define the at least one body tab. 
     
     
         50 . The field-effect transistor (FET) according to  claim 49 , wherein the FET is a silicon-on-insulator (SOI) FET, fabricated using a silicon-on-insulator (SOI) technology. 
     
     
         51 . The field effect transistor (FET) according to  claim 50 , wherein a silicon layer of the SOI FET is a thin-film silicon layer. 
     
     
         52 . The field-effect transistor (FET) according to  claim 51 , wherein the at least one body contact region is fully or partially contained within the source region. 
     
     
         53 . The field-effect transistor (FET) according to  claim 52 , further comprising an isolation region having the first conductivity type which isolates the at least one body contact region from one of the source and the drain region. 
     
     
         54 . The field-effect transistor (FET) according to  claim 51 , wherein the at least one body tab comprises two or more body tabs. 
     
     
         55 . The field-effect transistor (FET) according to  claim 54 , wherein the two or more body tabs are symmetrically placed along a width of the body region. 
     
     
         56 . The field-effect transistor (FET) according to  claim 51 , wherein the at least one body contact region comprises two or more body contact regions. 
     
     
         57 . The field-effect transistor (FET) according to  claim 53 , further comprising at least one isolation polysilicon structure configured to define the isolation region. 
     
     
         58 . The field-effect transistor (FET) according to  claim 57 , wherein the at least one polysilicon tab, the gate polysilicon structure, and the isolation polysilicon structure form a single polysilicon structure. 
     
     
         59 . The field-effect transistor (FET) according to  claim 51 , wherein the at least one body tab provides a resistive conduction path between the body region and the body contact, wherein resistance value of the resistive conduction path is adjusted via a length and a width of the at least one body tab. 
     
     
         60 . The field-effect transistor (FET) according to  claim 51 , further comprising a conductive contact atop a portion of the at least one body contact region. 
     
     
         61 . The field-effect transistor (FET) according to  claim 51 , wherein the transistor is a metal-oxide-semiconductor field effect transistor (MOSFET). 
     
     
         62 . The field-effect transistor (FET) according to  claim 50 , further comprising:
 an insulating layer; and   a silicon layer overlying the insulating layer,   wherein the drain region, the source region, the body region, the at least one body contact region, and the at least one body tab are formed in the silicon layer and extend through the silicon layer to reach the insulating layer.   
     
     
         63 . An integrated circuit (IC) comprising one or more of a) the field-effect transistor (FET) of  claim 3 , b) the multi-finger FET of  claim 24 , c) the FET of  claim 51 , d) the circuital arrangement of  claim 34 , and e) the transistor device of  claim 41 . 
     
     
         64 . A method for connecting a body region and a source region of a field-effect transistor (FET), the method comprising:
 resistively connecting, by at least one body tab extending through the source region of the FET, the body region of the FET to a body contact region in contact with the source region,   wherein the transistor is fabricated using a silicon-on-insulator (SOI) technology.   
     
     
         65 . The method according to  claim 64 , wherein the body tab, the body contact region and the body region have a same type doping.