Copper-containing c4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same

Abstract

The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device.

What is claimed is: 
     
         1 . A ball-limiting metallurgy (BLM) stack comprising:
 a copper pad on a surface of a semiconductor structure;   a metal containing layer disposed on the copper pad;   a copper stud disposed on the metal containing layer; and   a reflowed solder bump disposed on the copper stud, wherein the reflowed solder bump is at least partially covering sides of the copper stud, and wherein a lowermost portion of the reflowed solder bump is located above the metal containing layer.   
     
     
         2 . The ball-limiting metallurgy (BLM) stack of  claim 1 , wherein the reflowed solder bump includes tin and lead. The ball-limiting metallurgy (BLM) stack of  claim 1 , further including an intermetallic region at an interface between the copper stud and the reflowed solder bump. 
     
     
         4 . The ball-limiting metallurgy (BLM) stack of  claim 1 , further including a sputtered copper layer between the metal containing layer and the copper stud. 
     
     
         5 . The ball-limiting metallurgy (BLM) stack of  claim 1 , wherein the metal containing layer includes titanium. 
     
     
         6 . The ball-limiting metallurgy (BLM) stack of  claim 1 , wherein the metal containing layer includes an alloy of titanium and tungsten. 
     
     
         7 . A ball-limiting metallurgy (BLM) stack comprising:
 a copper pad on a surface of a semiconductor structure;   a titanium containing layer disposed on the copper pad;   a copper stud disposed on the titanium containing layer; and   a reflowed solder bump disposed on the copper stud, wherein the reflowed solder bump is at least partially covering sides of the copper stud, and wherein a lowermost portion of the reflowed solder bump is located above the titanium containing layer.   
     
     
         8 . The ball-limiting metallurgy (BLM) stack of  claim 7 , further including a sputtered cop layer between the titanium containing first layer and the copper stud. 
     
     
         9 . The ball-limiting metallurgy (BLM) stack of  claim 7 , wherein the reflowed solder bump includes tin and lead. 
     
     
         10 . The ball-limiting metallurgy (BLM) stack of  claim 7 , further including an intermetallic region at an interface between the copper stud and the reflowed solder bump. 
     
     
         11 . A semiconductor system comprising:
 a semiconductor structure, including:
 a copper pad on a surface of a semiconductor structure; 
 a titanium containing layer disposed on the copper pad; 
 a copper stud disposed on the titanium containing layer; 
 a reflowed solder bump disposed on the copper stud, wherein the reflowed solder bump is at least partially covering sides of the copper stud, and wherein a lowermost portion of the reflowed solder bump is located above the titanium containing layer; and 
   a flip chip, coupled to the reflowed solder bump of the semiconductor structure.   
     
     
         12 . The semiconductor system of  claim 11 , wherein the semiconductor structure is a chip-scale package. 
     
     
         13 . The semiconductor system of  claim 11 , wherein the flip chip is a chip-scale package format. 
     
     
         14 . The semiconductor system of  claim 11 , further including a sputtered copper layer between the titanium containing first layer and the copper stud. 
     
     
         15 . The semiconductor system of  claim 11 , wherein the reflowed solder bump includes tin and lead. 
     
     
         16 . The semiconductor system of  claim 11 , further including an intermetallic region at an interface between the copper stud and the reflowed solder bump. 
     
     
         17 . The semiconductor system of  claim 11 , wherein the titanium containing layer includes an alloy of titanium and tungsten.