Semiconductor device including shallow trench isolation structures

Abstract

A method for forming a semiconductor structure is provided. The method includes providing a substrate having a first region and a second region; and forming at least one first trench in the first region of the substrate, and at least one second trench in second region of the substrate. The method also includes forming a first liner layer on side and bottom surfaces of the first trench, and the side and bottom surfaces of the second trench; and performing a rapid thermal oxy-nitridation process on the first liner layer to release a tensile stress between the first liner layer and the substrate. Further, the method includes removing a portion of the first liner layer in the first region to expose the first trench; and forming a second liner layer on the side and bottom surface of the first trench.

1 .- 15 . (canceled) 
     
     
         16 . A semiconductor structure, comprising:
 a substrate having a first region and a second region;   at least one shallow trench isolation structure formed in the substrate in the first region;   at least one shallow trench isolation structure formed in the substrate in the second region;   a nitrided-oxidized first liner layer made from a first liner layer after a rapid thermal oxy-nitridation process to release a tensile stress between the first liner layer and the substrate, wherein the nitrided-oxidized first liner layer is formed between the substrate and the shallow trench isolation structure in the second region; and   a second liner layer formed between the shallow trench isolation structure and the substrate in the first region.   
     
     
         17 . The semiconductor structure according to  claim 16 , wherein:
 NMOS transistors are formed in the first region of the substrate; and   PMOS transistors are formed in the second region of the substrate.   
     
     
         18 . The semiconductor structure according to  claim 16 , wherein the shallow trench isolation structures are formed by:
 forming an isolation film on the first liner layer and the second liner layer; and   performing a planarization process on the isolation film until the surface of the substrate is exposed.   
     
     
         19 . The semiconductor structure according to  claim 16 ,
 the nitrided-oxidized first liner layer after the rapid thermal oxy-nitridation process includes silicon oxynitride; and   the first liner layer is made of silicon oxide, before the rapid thermal oxy-nitridation process.   
     
     
         20 . The semiconductor structure according to  claim 16 , wherein:
 the second liner layer is made of silicon oxide.   
     
     
         21 . The semiconductor structure according to  claim 16 , wherein:
 the first liner layer is formed by an in situ steam generation (ISSG) process.   
     
     
         22 . The semiconductor structure according to  claim 16 , wherein:
 the rapid thermal oxy-nitridation process includes a rapid thermal nitridation process and a rapid thermal oxidation process of the first liner layer.