Ultrasonic imaging compression methods and apparatus

Abstract

To implement a single-chip ultrasonic imaging solution, on-chip signal processing may be employed in the receive signal path to reduce data bandwidth and an output data module may be used to move data for all received channels off-chip as a digital data stream. The digitization of received signals on-chip allows advanced digital signal processing to be performed on-chip, and thus permits the full integration of an entire ultrasonic imaging system on a single semiconductor substrate. The on-chip digitization of received signals also enables the on-chip integration of ultrasound processing and/or pre-processing to reduce the burden on off-chip computing. Data compression architectures are disclosed to facilitate the transfer of data off-chip as a digital data stream in accordance with the bandwidth requirements of standard commercially-available output interfaces.

What is claimed is: 
     
         1 . An ultrasound device, comprising:
 at least one ultrasonic transducer element integrated on a semiconductor die;   an analog receive circuit integrated on the semiconductor die, the analog receive circuit arranged to receive an output signal from the at least one ultrasonic transducer element; and   a receive compression circuit integrated on the semiconductor die and configured to generate a compressed digital signal prior to any image reconstruction process being performed, the receive compression circuit comprising:
 a data reduction circuit having an input connected to an output of the analog receive circuit, the data reduction circuit configured to generate the compressed digital signal; and 
 a digital signal processing block in communication with the data reduction circuit, the digital signal processing block arranged to receive the compressed digital signal and perform at least a portion of an image reconstruction process; 
 wherein an output of the digital signal processing block is configured to be transmitted from the semiconductor die as a data stream. 
   
     
     
         2 . The ultrasound device of  claim 1 , wherein the data reduction circuit comprises:
 an analog compression circuit configured to receive the output of the analog receive circuit and perform analog pre-image reconstruction compression based on the output of the analog receive circuit to produce compressed analog pre-image reconstruction data;   an analog to digital converter (ADC) configured to convert the compressed analog pre-image reconstruction data to a digital representation; and   a digital compression circuit configured to receive the digital representation and reduce a data bandwidth of the digital representation, thereby producing the compressed digital signal.   
     
     
         3 . The ultrasound device of  claim 2 , wherein the analog compression circuit further comprises a low-pass filter configured to provide anti-aliasing of the output of the analog receive circuit. 
     
     
         4 . The ultrasound device of  claim 3 , wherein the low-pass filter has a cutoff frequency selected from the group consisting of: on the order of 5 MHz, on the order of 10 MHz, on the order of 25 MHz, and on the order of 50 MHz. 
     
     
         5 . The ultrasound device of  claim 2 , wherein the ADC comprises one more of: a successive approximation register (SAR) ADC, a flash ADC, a pipeline ADC, a sigma-delta ADC, a multi-slop ADC, and a time-interleaved ADC. 
     
     
         6 . The ultrasound device of  claim 5 , wherein the ADC comprises a 10-bit ADC configured to operate at a conversion rate selected from the group consisting of: 20 mega-samples per second (Msps), 40 Msps, 50 Msps, and 80 Msps. 
     
     
         7 . The ultrasound device of  claim 2 , wherein the digital compression circuit is configured to perform one or more of: quadrature demodulation, downsampling, quadrature sampling, filtered downsampling, cascade integrating comb (CIC) filtering, receive aperture filtering, polyphase filtering, re-quantization, and pulse compression. 
     
     
         8 . The ultrasound device of  claim 7 , wherein the digital compression circuit comprises a filter, a decimation circuit, a re-quantization circuit, and an arithmetic logic unit (ALU), wherein an output of the filter is coupled to an input of the decimation circuit, an output of the decimation circuit is coupled to an input of the re-quantization circuit, and an output of the re-quantization circuit is coupled to an input of the ALU. 
     
     
         9 . The ultrasound device of  claim 2 , wherein the digital compression circuit comprises quadrature demodulation circuitry configured to generate the compressed digital signal. 
     
     
         10 . The ultrasound device of  claim 2 , wherein the digital compression circuit comprises down-sampling circuitry configured to generate the compressed digital signal. 
     
     
         11 . The ultrasound device of  claim 2 , wherein the digital compression circuit comprises filtering circuitry configured to generate the compressed digital signal. 
     
     
         12 . The ultrasound device of  claim 11 , wherein the filtering circuitry comprises a cascade integrating comb (CIC) filter configured to generate the compressed digital signal. 
     
     
         13 . The ultrasound device of  claim 2 , wherein the digital compression circuit comprises re-quantization circuitry configured to generate the compressed digital signal. 
     
     
         14 . The ultrasound device of  claim 2 , wherein the digital compression circuit comprises an arithmetic logic unit configured to generate the compressed digital signal. 
     
     
         15 . The ultrasound device of  claim 14 , wherein the arithmetic logic unit is configured to perform at least one operation to generate the compressed digital signal selected from the group consisting of: extending a word size, bit shifting, accumulating, and subtracting. 
     
     
         16 . The ultrasound device of  claim 2 , wherein the digital compression circuit is configured to generate the compressed digital signal based, at least in part, on a mode of operation of the ultrasound device. 
     
     
         17 . The ultrasound device of  claim 1 , wherein the digital signal processing block comprises:
 an image formation circuit; and   a post-processing circuit.   
     
     
         18 . The ultrasound device of  claim 17 , wherein the image formation circuit is configured to perform the at least a portion of an image reconstruction process. 
     
     
         19 . The ultrasound device of  claim 17 , wherein the image formation circuit is configured to perform the at least a portion of an image reconstruction process using a beamforming technique. 
     
     
         20 . The ultrasound device of  claim 19 , wherein the beamforming technique comprises using an integrated backprojection technique, in which at least one of receiver time-of-flight values and receive apodization values are reused within consecutive scans. 
     
     
         21 . The ultrasound device of  claim 17 , wherein the post-processing circuit is configured to perform additional data compression beyond that used to generate the compressed digital signal prior to any image reconstruction process being performed. 
     
     
         22 . The ultrasound device of  claim 1 , further comprising a memory integrated on the semiconductor die, the memory configured to temporarily store the output of the digital signal processing block, prior to being transmitted from the semiconductor die. 
     
     
         23 . The ultrasound device of  claim 22 , wherein the memory is further configured to directly receive at least some output from the data reduction circuit, not processed by the digital signal processing block. 
     
     
         24 . The ultrasound device of  claim 1 , further comprising an output interface configured to output the data stream from the semiconductor die. 
     
     
         25 . The ultrasound device of  claim 24 , wherein the output interface is a high-speed serial interface selected from the group consisting of a USB 3.0 interface, a USB 3.1 interface, a USB 2.0 interface, a Thunderbolt interface, a FireWire interface, and a Gigabit Ethernet interface.