Silicon Heat-Dissipation Package For Compact Electronic Devices

Abstract

Embodiments of a silicon heat-dissipation package for compact electronic devices are described. In one aspect, a device includes first and second silicon cover plates. The first silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The second silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The first primary side of the second silicon cover plate includes an indentation configured to accommodate an electronic device therein. The first primary side of the second silicon cover plate is configured to mate with the second primary side of the first silicon cover plate when the first silicon cover plate and the second silicon cover plate are joined together with the electronic device sandwiched therebetween.

What is claimed is: 
     
         1 . A method, comprising:
 forming features of one or more first silicon cover plates on a first silicon wafer;   forming features of one or more second silicon cover plates on a second silicon wafer;   forming features of one or more first silicon heat sinks on a third silicon wafer;   forming features of one or more second silicon heat sinks on a fourth silicon wafer;   joining the first, the second, the third, and the fourth silicon wafers into a stack of wafers with one or more electronic devices sandwiched between the first silicon wafer and the second silicon wafer, such that:
 the first and the second wafers are sandwiched between the third and the fourth wafers, 
 the first wafer is adjacent the fourth wafer, 
 the second wafer is adjacent the third wafer, 
 the one or more first silicon cover plates, the one or more second silicon cover plates, the one or more first silicon heat sinks, and the one or more second silicon heat sinks are aligned with each other, and 
 each of the one or more electronic devices is sandwiched between a respective one of the first silicon cover plates and a respective one of the second silicon cover plates; and 
   dicing the stack of wafers to form one or more silicon heat-dissipation packages each of which having a respective one of the one or more electronic devices embedded therein.   
     
     
         2 . The method of  claim 1 , wherein at least one of the one or more electronic devices comprises a light-emitting diode (LED), a laser diode, a radio frequency (RF) chip, a microwave chip, a photodiode, or a sensor. 
     
     
         3 . The method of  claim 1 , wherein forming features of one or more first silicon cover plates on the first silicon wafer comprises forming an opening on each of the one or more first silicon cover plates, the opening communicatively connecting a first primary side and a second primary side of the first silicon cover plate opposite the first primary side, the opening aligned with a respective one of the one or more electronic devices and exposing at least a portion of the respective electronic device. 
     
     
         4 . The method of  claim 3 , further comprising:
 disposing each of one or more collimation elements in the respective opening of a respective one of the one or more first silicon cover plates.   
     
     
         5 . The method of  claim 4 , wherein at least one of the one or more collimation elements comprises a lens made of glass, silicone, quartz, or polymer. 
     
     
         6 . The method of  claim 1 , wherein forming features of one or more second silicon cover plates on the second silicon wafer comprises forming an indentation on a primary side of each of the one or more second silicon cover plates, the indentation configured to accommodate a respective one of the electronic devices therein. 
     
     
         7 . The method of  claim 1 , wherein forming features of one or more first silicon heat sinks on the third silicon wafer comprises forming a plurality of first grooves that form a plurality of first fins on a primary side of each of the one or more first silicon heat sinks facing away from and not contacting a respective one of the one or more second silicon cover plates. 
     
     
         8 . The method of  claim 1 , wherein forming features of one or more second silicon heat sinks on the fourth silicon wafer comprises forming an opening on each of the one or more second silicon heat sinks, the opening communicatively connecting a first primary side and a second primary side of the second silicon heat sinks opposite the first primary side, the opening of each of the one or more second silicon heat sinks aligned with the opening of a respective one of the one or more first silicon cover plates. 
     
     
         9 . The method of  claim 1 , wherein forming features of one or more second silicon heat sinks on the fourth silicon wafer comprises forming a plurality of second grooves that form a plurality of second fins on a primary side of each of the one or more second silicon heat sinks facing away from and not contacting a respective one of the one or more first silicon cover plates. 
     
     
         10 . The method of  claim 1 , wherein forming features of the one or more first silicon cover plates on the first silicon wafer, forming features of the one or more second silicon cover plates on the second silicon wafer, and forming features of the one or more first silicon heat sinks on the third silicon wafer comprise forming electrically-conductive features on each of the one or more first silicon cover plates, each of the one or more second silicon cover plates, and each of the one or more first silicon heat sinks such that the respective electronic device in each of the one or more silicon heat-dissipation packages is configured to be powered by an external power source through the electrically-conductive features on the respective first silicon cover plate, the respective second silicon cover plate, and the respective first silicon heat sink. 
     
     
         11 . A method, comprising:
 joining first, second, third, and fourth silicon wafers into a stack of wafers with one or more electronic devices sandwiched between the first silicon wafer and the second silicon wafer, such that:
 the first and the second wafers are sandwiched between the third and the fourth wafers, 
 the first wafer is adjacent the fourth wafer, and 
 the second wafer is adjacent the third wafer; and 
   dicing the stack of wafers to form one or more silicon heat-dissipation packages each of which having a respective one of the one or more electronic devices embedded therein.   
     
     
         12 . The method of  claim 11 , further comprising:
 forming features of one or more first silicon cover plates on the first silicon wafer;   forming features of one or more second silicon cover plates on the second silicon wafer;   forming features of one or more first silicon heat sinks on the third silicon wafer; and   forming features of one or more second silicon heat sinks on the fourth silicon wafer.   
     
     
         13 . The method of  claim 12 , wherein the one or more first silicon cover plates, the one or more second silicon cover plates, the one or more first silicon heat sinks, and the one or more second silicon heat sinks are aligned with each other, and wherein each of the one or more electronic devices is sandwiched between a respective one of the first silicon cover plates and a respective one of the second silicon cover plates. 
     
     
         14 . The method of  claim 11 , wherein the first silicon wafer comprises features of one or more first silicon cover plates thereon, the features comprising an opening on each of the one or more first silicon cover plates, the opening communicatively connecting a first primary side and a second primary side of the first silicon cover plate opposite the first primary side, the opening aligned with a respective one of the one or more electronic devices and exposing at least a portion of the respective electronic device. 
     
     
         15 . The method of  claim 14 , further comprising:
 disposing each of one or more collimation elements in the respective opening of a respective one of the one or more first silicon cover plates,   wherein at least one of the one or more collimation elements comprises a lens made of glass, silicone, quartz, or polymer.   
     
     
         16 . The method of  claim 11 , wherein the second silicon wafer comprises features of one or more second silicon cover plates thereon, the features comprising an indentation on a primary side of each of the one or more second silicon cover plates, the indentation configured to accommodate a respective one of the electronic devices therein. 
     
     
         17 . The method of  claim 11 , wherein the third silicon wafer comprises features of one or more first silicon heat sinks thereon, the features comprising a plurality of first grooves that form a plurality of first fins on a primary side of each of the one or more first silicon heat sinks facing away from and not contacting a respective one of the one or more second silicon cover plates. 
     
     
         18 . The method of  claim 11 , wherein the fourth silicon wafer comprises features of one or more second silicon heat sinks thereon, the features comprising an opening on each of the one or more second silicon heat sinks, the opening communicatively connecting a first primary side and a second primary side of the second silicon heat sinks opposite the first primary side, the opening of each of the one or more second silicon heat sinks aligned with the opening of a respective one of the one or more first silicon cover plates. 
     
     
         19 . The method of  claim 11 , wherein the fourth silicon wafer comprises features of one or more second silicon heat sinks thereon, the features comprising a plurality of second grooves that form a plurality of second fins on a primary side of each of the one or more second silicon heat sinks facing away from and not contacting a respective one of the one or more first silicon cover plates. 
     
     
         20 . The method of  claim 12 , wherein forming features of the one or more first silicon cover plates on the first silicon wafer, forming features of the one or more second silicon cover plates on the second silicon wafer, and forming features of the one or more first silicon heat sinks on the third silicon wafer comprise forming electrically-conductive features on each of the one or more first silicon cover plates, each of the one or more second silicon cover plates, and each of the one or more first silicon heat sinks such that the respective electronic device in each of the one or more silicon heat-dissipation packages is configured to be powered by an external power source through the electrically-conductive features on the respective first silicon cover plate, the respective second silicon cover plate, and the respective first silicon heat sink.