Memory Controller For Selective Rank Or Subrank Access

Abstract

A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

What is claimed is: 
     
         1 . A memory controller, comprising:
 at least one transaction queue to direct memory commands to first and second memory devices as a unified rank in a first mode, and to direct memory commands to the first and second memory devices as respective subranks in a second mode;   a command bus interface to direct the memory commands to the memory devices via a shared command bus;   a data bus interface having a width with a first portion of the width to be coupled to the first memory device but not the second memory device and a second portion of the width to be coupled to the second memory device but not the first memory device; and   circuitry to associate data exchanged via both of the first portion and the second portion with each of the memory commands in the first mode, and to associate data exchanged via an exclusive one of the first portion and the second portion with respective memory commands in the second mode.